Error Reset and Self-Test Circuits

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

It should be noted that a count up enable from the divide-

the temperature alarm circuit on the front panel. The

by-16 threshold counter occurs once for each 16, 160,

reset signal through OR gate U17 develops error reset

1600, or 16, 000 overhead data bits as determined by

signals DERRS and DERRS- that reset the diagnostic

the setting of the error rate threshold switches. The 16-

circuits on the demultiplexer cards. The error reset latch

bit interval corresponds to a switch setting of 1 error per

is reset by signal ERSTSW- when the front panel

10 bits; the 160-bit interval corresponds to a switch

DISPLAY RESET switch is released.

setting of 1 error per 100 bits, etc. Thus, for example, if

the error rate threshold switches were set for 1 error in

5-546. When the front panel SELF TEST switch is set

10 bits and no errors were being detected, the error

to the on (up) position, self-test switch signal STS- is

up/down counter would be incremented only once per 16

applied to the ERD card, setting the self-test latch. At

over- head data bits. The apparent difference between

this time, self-test signals ST1- and ST2- are produced

the 1-in-10 error rate threshold selected by the switches,

to set the diagnostic circuits on all the cards in the

and the 1-in-16 rate for incrementing the error up/ down

multiplexer set to their self-test mode. When the SELF

counter is due to the statistical nature of the error rate

TEST switch is set to the off (down) position, self-test

measurement approach. Statistically, measuring zero

one-shot multivibrator U12 is triggered on for

errors in 16 bits provides approximately 80 percent

approximately 10 seconds to hold the logic circuits in a

confidence that the error rate among all received data

reset condition until the diagnostic circuits have time to

bits is no worse than 1 in 10. Similarly, one bit of

resettle to the no-error state.

detected error during a 16-bit interval indicates an error

rate of 1 in 10 at a confidence level of approximately 50

5-547. Loss

frame

synchronization

causes

percent. Therefore, when a given error rate switch

demultiplexer frame sync signal DFS to go low. This

setting is selected, and the front panel LINK ERROR

condition produces error reset signals DERRS and

RATE indicator is out, the operator can be approximately

DBRRS- from OR gate U17. At the same time that

80 percent confident that the overall error rate of the

signal DFS goes low, frame sync one-shot multivibrator

incoming data stream is no worse than the threshold

U12 is triggered on for approximately 0.5 second. The

value selected.

resulting delay inhibits the diagnostic circuits while the

demultiplexer

attempts

reestablish

frame

synchronization.

5-545. Error Reset and Self-Test Circuits (Figure 5-

41). The error reset function in the multiplexer set is

5-548. Remote Alarm Circuits (Figure 5-41). Six

initiated when the front panel DISPLAY RE-SET switch is

remote alarm circuits on the ERD card provide

pressed.

At this time, error reset switch signal

operational status signals to the REMOTE ALARM

ERSTSW- is applied to the ERD card, which sets the

connector on the rear panel. The six signals can be

error reset latch. If the front panel SELF TEST switch is

routed to a remote location for monitoring purposes.

set to the off (down) position, AND gate U26-3 is enabled

Five of the six signals are generated by energizing an

and causes error reset signals ERST- and ERST, and

associated remote alarm relay (K1 through K5) to

reset temperature alarm signal RTA to be generated to

provide a closed-loop condition when an error condition

re- set their associated diagnostic circuits to their off

exists.

positions. Signals ERST- and ERST reset the diagnostic

circuits on the multiplexer cards and signal RTA resets

Change 1 5-146