Figure 5-40. ERD Card, Minor Frame Generation Circuits

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

Figure 5-40. ERD Card, Minor Frame Generation Circuits - Block Diagram

In turn, the 4-bit output (bits L through 4) from the

DMFC4) from the minor frame counter are applied to the

overhead shift register plus on-line signal DOD- (bit 5)

A inputs on the minor frame comparator. The minor

are applied to the B inputs of the minor frame

frame comparator continually compares the two 5-bit

comparator. Bits 1 through 4 are also applied to the

inputs, and when they are identical, an A=B signal is

preset inputs of the minor frame counter. Bit 5 is applied

generated and applied to enable AND gate U27-8 and

to the counter through the counter control circuit. The 5-

inhibit AND gate U27-6 in the input of the error up/down

bit minor frame count output signals (DMFCO through

counter.

5-143