|
|
T.O. 31W2-2GSC24-2
TM 11-5805-688-14-1
NAVELEX 0967-LP-545-3011
Word signal W28 causes the appropriate AND gate to be
5-532. Diagnostic Circuits. Frame sync diagnostic
enabled and the AND gate applies a count up or count
signal FSD- is generated when an error signal is applied
down signal to U37 during word 28. The error up/down
to OR gate U12-4 from the VLSR diagnostic circuits or
counter is initially set to a count of five, and as long as it
when an error signal is applied to OR gate U12-4 from
contains a count of five, AND gate U28-8 inhibits AND
the stuff command code compare circuits. Word counter
gate U34-6 so that the maximum count in U37 is held to
U47 in the VLSR diagnostic circuits is clocked by the
five. When U37 contains a count between one and four,
half-rate clock- signal from flip-flop U56-6. The word
a count up signal can be applied through AND gate U34-
counter is incremented one count when it is clocked and
6 to make U37 count up. In turn, each count down
signal A=B is applied from comparator U65. Each time
signal applied through AND gate U59-6 decrements the
the word counter reaches a full count of 15, it generates
count in U37 by one. When the count is decremented to
a terminal count (TC) output that is applied to AND gate
a zero count and word signal W28 occurs, loss-of-frame
U53-12. The TC output also resets the counter to a
flip-flop U29-9 is clocked by signal DEOS2- and
count of six. The preset to a count of six causes the
demultiplexer loss of frame sync signal DLOF- is
counter to produce a TC output after a count of 10. AND
generated. At the same time, frame sync flip-flop U29-6
gate U53-12 is enabled during the write cycle of the
is also clocked and signal DFS goes low and inhibits
VLSR. When a TC is generated, a clock signal is
AND gates U34-6 and U59-6 in the in- puts to U37.
generated to flip-flops U10-6 and U10-8 that function as
When signal DFS goes low, the output from OR gate
a latch circuit. At this time, the SD2 and SD3 data bits
U52-4 goes high and releases the inhibit condition (clear)
being applied to R.A.M. No. 1 in the VLSR are locked
to latch U54. The output from U29-7 goes high and
into the two latches. Therefore, when the two data bits
removes the inhibit (clear) on flip-flop U26. These
(SD2 and SD3) are processed through the shift register
actions enable the parallel frame sync acquisition
and applied back to exclusive OR gates U18-3 and U18-
functions/circuits.
11, a reverse compare should be present to place high
inputs to OR gate U19. The reverse compare is a
5-531.
Positive stuff command flip-flop U27-6 or
deliberate mismatch of the signals applied to the two
negative stuff command flip- flop U27-8 provides signal
exclusive OR gates. The data outputs from the two
DNSE or DPSE to the ERD card and the GC/DM card to
latches are inverted while the B10 data bits applied to the
indicate that the minor frame being monitored contains a
two exclusive OR gates are of the opposite polarity when
positive stuff, negative stuff, or no-action code. When
the VLSR is in a no-error condition. Therefore, in an
both signals are low, the no-action command code is
error condition, one of the exclusive OR gates has a
indicated. When a positive stuff code is successfully
compare that is applied through OR gate U19-6 to flip-
monitored (error count less than eight) the count eight
flop Ull. The flip-flop, in turn, produces a high output to
(Q3) output from error bit counter U44 is low. This
OR gate U12-4 to produce signal FSD-.
causes U27-8 to produce DPSE when signal DW28
occurs during word 28. In turn, a negative stuff code
5-533. AND gates U28-3, U20-10, U20-4, U20-1, and
circuit produces signal DPSE when a negative stuff code
U20-13 monitor the frame sync maintenance circuits and
is successively decoded and contains less than eight
cause frame sync diagnostic error signal FSD- to be
errors.
generated when the circuits are in an error condition.
5-141
|
Privacy Statement - Press Release - Copyright Information. - Contact Us |