Once signal DSYNC-CONT.

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

The bit counter output associated with the AND gate

maintenance function. Signal DFS- also holds flip-flop

(U59-12, U59-8, or U60-8) that is enabled by the

U26 in a clear state, which, in turn, causes U26 to

parallel sync signal from latch U62 is the active counter.

apply a constant (clear) signal that disables latch U62.

At this time, the other two counters are counting the

At this time, the FS card switches from the frame sync

errors, but the two AND gates receiving the error

acquisition function to the frame sync maintenance

counters are inhibited by low-level inputs from latch U62.

function.

Should the bit error counter (U42, U43, or U44) that is

activated reach an error count of three, the AND gate

5-529. In the frame sync maintenance function, bit 0 in

(U59-12, U59-8, or U60-8) is enabled by the sync

each word of the in- coming data (SD3) is monitored

enable signal and the count one and count two inputs

during words 1 through 23. During word 28, the outputs

from the bit error counter. The low output from the

of the three bit error counters are monitored through OR

enabled AND gate is applied through OR gate U60-12 to

gate U58-8. In this mode of operation, all three bit error

one input of AND gate U28. When demultiplexer end-of-

counters are operational and the output from each one

scan signal DEOS2 occurs, the output from U28 sets

supplies an error count to a decode circuit consisting of

flip-flop U26, which, in turn, clears latch U62. Latch

two AND gates, one OR gate, and one inverter. Each

U62 then forces the output of OR gate U53-8 to go high,

decode circuit, in turn, supplies a low-level error signal

which causes the out- put of OR gate U52-4 to go high,

to OR gate U58-8 when the counter contains an error

enabling latch U54. This action permits the parallel sync

count that is eight or higher. Seven or less errors

acquisition circuit to effectively start another parallel sync

detected during the check of bit 0 in words 1 through 23

acquisition search during word 1 of the next minor frame.

is acceptable. Therefore, in proper operation, two of the

decoder circuits apply low inputs (high error counts) to

5-528. When the serial search during words 12 through

OR gate U58-8, and the third input from the decoder

23 is successful, the output from the enabled AND gate

circuit associated with the error bit counter that is

(U60-8, U59-8, or U59-12) remains high and the reset

monitoring the appropriate stuff command codes is a

function described previously is inhibited. When word

high input (less than eight errors) to the OR gate.

signal DW28 is generated, AND gate U60-6 in the input

circuit of frame sync flip-flop U29 has high enable signals

FS- from the Q out- put of U29 and a high enable parallel

5-530. In normal operation, the output from OR gate

sync (PS) signal from OR gate U53. When word signal

U58-8 is applied through inverter U35-2 to the input of

W28 occurs up/down counter U37 is preset to a count of

AND gate U34-6 that is connected to the count up input

five. At the same time, the high output through inverter

of error up/down counter U37. The output from OR gate

U36-12 sets U29 to produce de- multiplexer frame sync

U58-4 is also applied to AND gate U59-6 that is

signal DFS when U29 is clocked by signal DEOS2-.

connected to the count down input of U37. Therefore,

Signal DFS places an enable input to AND gates U34

when an error count of less than eight is monitored

and U59 in the inputs to error up/ down binary counter

during words 1 through 23 of a given minor frame, a

U37. Signal DFS also forces OR gate U52 to inhibit latch

count up signal is applied to AND gate U34-6. In turn,

U54 by holding U54 in a clear state. Signal FS from flip-

more than seven errors cause a count down signal to be

flop U29-7 disables AND gate U60 to prevent error

applied to AND gate U59-6.

up/down counter U37 from being reset in the frame sync

5-140