DETAILED CIRCUIT DISCUSSION-CONT. - TM-11-5805-688-14-10238

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

5-516. In the parallel maintenance function, each data

the output count of counter U57 to 0000. The A=B signal

bit in 10 consecutive data words is monitored for the

from comparator U65 determines the number of

presence of one of the three stuff command codes

addresses applied to the R.A.M.'s. To service 32 bit

contained in the bit 0 positions of the first 10 words of the

locations in the R.A.M.'s, an A=B signal after a count of

incoming message format. At the time that the VLSR is

16 is required; to service 20 bit locations, a count of 10

enabled, the circuits on the FS card do not know which

is required. Half-rate flip- flop U56-5 is toggled by RIO-

words they are monitoring in the incoming message

to produce the half-rate clocks to counter U57 and the

format. The first words monitored could be any bit

half-rate write enable signals to AND gate U55-11.

sequence within any 10-word sequence. The VLSR, in

effect, serially processes, at word level, 10 consecutive

5-518. Each R.A.M. services two pairs of data inputs

words while per- forming a parallel search of each bit

(SD3, SD2). Each data bit is temporarily stored in a

location in each word. Each R.A.M. in the VLSR holds

memory location for one data word time (between 16 and

two sets of data bits that are the equivalent of two

32 bit times). During each word time, a review of data

consecutive data words containing between 16 and 32

bits equivalent to one word length is written into each set

data bits. In one word time, each data bit in each of the

of R.A.M. memory locations. The result is data bits for

two sets stored in each of the R.A.M.'s is scanned in

one word being shifted serially to the adjacent R.A.M.

parallel, one bit at a time. After the equivalent of one

memory locations. Each pair of parallel outputs (SD3,

data word is scanned, the bits in each data word

SD2) in each R.A.M. being serviced is applied as inputs

location (DO, D1, D2, D3) are shifted (B1 becomes B2,

to a 6-bit storage register (U40, U32, U24, or U9). The

B8 becomes B9, etc) and the next parallel search is

high enable signal from U56 to AND gate U55-11 is also

performed. This process continues until a compare is

applied as the latch signal to the four storage registers

made as described in the following paragraphs.

(U40, U32, U24, and U9). At this time, the four data

bit outputs from the R.A.M.'s are latched into the

5-517. The odd-bit shift register circuits in the VLSR are

registers. One-half RIO time later, a high RIO is applied

disabled when the LSB (DPUBO) of the applied 5-bit

to the second input of AND gate U55-11 and a low-level

ports- in-use signals is a one, representing an odd

write enable is applied to each R.A.M. to initiate the next

number. The low signal out of inverter U36-4 holds odd-

write function.

bit flip-flop U64-5 in a preset condition and the signal

makes the LSB of the preset countered in 4-bit address

5-519. The data bits latched into the four storage

counter U57 a zero. With flip-flop U64-5 held in a high

registers (U40, U32, U24, and U9) are applied to the

state, half-rate flip-flop U56-5 increments the counter to

Al, A2 (SD3) and B1, B2 (SD2) inputs of data selectors

generate a different address to the five R.A.M.'s (U49,

U48, U31, U23, U16, and U8. The B select input to

U41, U33, U25, and U17) every other RIO time. When

each data selector is held at a low level by the Q output

the counter output reaches a count that compares with

from odd-bit address flip-flop U64-9. The A input of each

the count pro- vided to address comparator U65 by

data selector is alternately enabled at the system clock

signals DPUB1, DPUB2, DPUB3, and DPUB4, the ad-

rate by Q output (half-rate clock-) from half-rate

dress comparator generates an A=B signal that presets

generator flip-flop U56-6.

Change 1 5-137