DETAILED CIRCUIT DISCUSSION

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

In an error condition, the compare condition is not

signals from U1 and U2 are applied to data flip-flop U4.

obtained and an error signal is applied through an OR

When the switch is in the LOOP position, the data and

gate to produce signal FSD- that is applied as an error

timing signals from the multiplexer portion of the same

input to the display card.

multiplexer set are applied to the data flip-flop for test

purposes. The data and timing from the multiplexer in

5-509. The stuff command code compare circuits

the loopback configuration are usable only when the

effectively compare the positive stuff code and negative

multiplexer and demultiplexer in a multiplexer set are

stuff code signals being generated in the sync

configured the same; i.e., for duplex operation.

maintenance circuits. An error condition exists when

both stuff codes are detected within the circuits at the

5-514. The incoming data are clocked through flip-flop

same time. During any one minor frame period being

U4-6 and the data channel output shift register formed by

monitored, only one stuff command will be in the

flip-flops U4-9, U5-5, and U5-9. The shift register

overhead message. When an error is detected, a

function is inhibited when signal FS (DFS) applied to U5-

diagnostic error signal is applied through an OR gate as

10 is low. Signal FS is low when the demultiplexer frame

signal FSD-.

synchronization is not established. The data output from

the shift register is applied through four parallel inverters

5-510. The second diagnostic error signal, LBS-, is

U3 to produce parallel output signals DTI1- through

generated when demultiplexer frame sync signal

DTI4- that are the data inputs to the active channel cards

DSYNC- is generated and the signal is not in

in the demultiplexer. The data output from flip-flop U4-6

synchronization with the parallel sync control circuits.

is also applied to data shift register U13, which produces

signals SD2 and SD3 that are used in the frame

synchronization function. U13 contains quad flip-flop

5-511. DETAILED CIRCUIT DISCUSSION.

circuits that are configured as a serial-in, parallel-out

shift register. Signals SD2 and SD3 are sequential data

5-512. The logic diagram associated with this detailed

bit outputs wherein SD2 is a data bit delayed one RIO

circuit discussion is contained in the circuit diagrams

time and SD3 is a data bit delayed two RIO times.

manual. The input data pulses (DATA+ and DATA-) are

applied through switches S1 and S4 to data receiver U1,

where the data pulses are conditioned to a TTL logic

5-515. Signals SD2 and SD3 from U13 is applied as an

level compatible with the logic on the FS card. DATA

input to R.A.M. No. 1 (U49) in the VLSR that is used in

switch S4 in the input circuit of U1 is set to the 75 or 6K

the parallel sync acquisition function, and as inputs to

(ohms) position as required by the circuit configuration.

U10 in the diagnostic function. Signal SD3 is also

The function of DATA switch S1 is to change the phase

applied as input Bll to the three command code

relationship of the inputs to meet different system

comparators (U14-1), and as an input to data-in flip-flop

equipment configurations.

U61 in the parallel and serial sync acquisition function. In

the following discussions, processing of the incoming

5-513.

The input timing pulses (TM+ and TM-)

data in the parallel sync acquisition circuits is described,

associated with the input data are conditioned to a TTL

and then processing of data in the serial sync acquisition

logic level in timing receiver U2. The conditioned timing

and sync maintenance circuits is described.

pulses from the circuit are applied through LOOPBACK

switch S3 to clock data flip-flop U4. When switch S3 is

in the NORM position, the incoming data and timing

5-136