Diagnostic Block Diagram Discussion

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

The bit error counter associated with the code

eight sets the associated flip-flop to produce a low-level

comparator that is monitoring the active stuff command

DPSE or DNSE signal. When both counters contain a

code being applied indicates between zero and seven

count of eight, the outputs from the two flip-flop are low.

errors when proper synchronization is present. When this

A high-level DPSE signal is applied to the ERD and

condition is met, a low-level signal applied to OR gate

GC/DM cards when a positive stuff command is decoded

U58 causes a high-level count up signal to the error

or a high-level DNSE signal is applied when a negative

count up/down binary counter during word 28. When all

stuff command is decoded.

A no-action code is

three bit counters contain counts of eight or more errors,

indicated when signals DPSE and DNSE are low.

all inputs to the OR gate are high and a low-level count

down signal is applied to the binary counter.

5-507.

The word reset flip-flop generates the

demultiplexer word counter reset when signal DSYNC- is

5-505. The error up/down binary counter is initially

applied. The signal is applied to the GC/DM card as a

enabled by signal DFS when frame sync acquisition is

synchronous timing signal that causes bit 0 of word 12 to

obtained. At this time, the counter output is preset to a

be generated at the same time bit 0 of word 12 of the

count of five. During word 28, the applied count up or

incoming data occurs.

count down signal applied through the OR gate is

clocked into the error up/down binary counter. The

5-508. Diagnostic Block Diagram Discussion (Figure

counter has a maximum count limit of five and can only

5-39). Two diagnostic error signals can be generated by

count upwards in the count up mode when its output is

the circuits on the FS card: frame sync diagnostic error

between one and four. Therefore, the maximum

signal FSD- and loss of frame sync diagnostic error

number of successive count down signals required to

signal LBS-. Signal FSD- can be initiated by the VLSR

initiate a loss of frame condition would be five. When the

circuits during the frame acquisition period of operation

counter reaches a count of zero, the count 0 causes the

or by the stuff command code compare circuits during

loss of frame flip-flop to generate demultiplexer loss of

the frame sync maintenance period of operation. In the

frame signal DLOP when the next end of scan signal

frame synchronization period of operation, the word

DEOS2- occurs. The count 0 also causes signal DFS

counter in the VLSR diagnostic circuits is incremented

from the frame sync flip-flop to go low and remove the

each time the A=B signal is generated from the address

inhibit to the parallel sync acquisition circuits so that

comparator in the VLSR circuits. The word counter is

another parallel sync acquisition search is performed.

configured to generate a TC output every 10 counts.

Ten counts are obtained by the TC output presetting the

5-506. During normal operation, the count eight outputs

counter to six, which is the time it takes a pair of SD2

from the positive stuff and negative stuff error counters

and SD3 data bits to be processed through the VLSR

are used to identify the stuff command code contained in

and returned to the diagnostic circuits. A TC condition is

the overhead message being monitored. When one of

obtained after 10 counts so that the TC output signal

the two bit error counters has an error count between

clocks latches No. 1 and No. 9. When clocked, the

zero and seven, the associated positive stuff or negative

latches contain the pair of SD2 and SD3 data bits applied

stuff command flip-flop output is set by word 28 signal

to the input of the VLSR (R.A.M. No. 1).

DW28 to produce a high-level DNSE or DPSE signal. In

turn, the bit error counter output that contains a count of

5-134