Serial Sync Acquisition and Sync Maintenance Circuits Block Diagram Discussion

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

At the time that signal SD3- is clocked into odd-bit shift

is achieved, the 12 bits sampled should compare.

When the comparator detects three or more errors

registers are shifted one bit. At this time, the half-rate

during words 12 through 23, the associated error

clock- signal and the odd-bit enable signal are applied to

counter generates an error reset signal that is applied

the A and B ad- dress inputs of the five data selectors.

through OR gate U60 to the parallel sync acquisition

The C1 and C2 inputs are enabled so that the parallel B1

circuits. This condition initiates another parallel sync

through B10 outputs contain a parallel readout of the odd

acquisition function and inhibits the start of the sync

data bit. In the next RIO time, the primary shift register

maintenance function. At the same time, the parallel

is enabled and processes the next consecutive sets of

sync enable signal applied to the AND gate is removed

data bits whose total is an even number of bits between

and the frame sync flip-flop cannot generate signal DFS.

16 and 32.

When two or less errors are counted during words 12

through 23, the error reset signal is not generated and

the input to the, AND gate remains enabled. When word

5-502.

Serial Sync Acquisition and Sync

28 timing signal DW28 is applied to the AND gate, the

Maintenance Circuits Block Diagram Discussion

frame sync flip-flop is set, signal DFS is generated, and

(Figure FO-9). In the sync acquisition function, signal

the parallel sync acquisition function is inhibited. Timing

DSYNC- resets the three bit error counters to zero. At

signal DW2429 during words 24 through 29 prevents a

the same time, the parallel sync enable signal is applied

further count from the three bit error counters after word

to one input of the AND gate in the input circuit of the

23. In turn, timing signal DW29- resets the error counter

frame sync flip-flop. The enable signal remains until

outputs to zero.

signal DFS is generated as described in the following

paragraph. The data in bit 0 of words 12 through 23 in

data input SD3 from the parallel sync acquisition circuits

5-504. The presence of signal DFS indicates that the

are clocked through the data-in flip-flop to the three code

sync acquisition function is complete and the sync

comparators. Bit 0 is selected by a combination of clock

maintenance function is being performed. During sync

signal RIO and demultiplexer end-of-scan signal DEOS2

maintenance, each of the three code comparators is

that enable an AND gate to clock the data-in flip-flop.

active and continually performs a serial compare of the

The over- head data pulses (bit 0) are also applied as

incoming data in bit 0 of words 1 through 23 with the

overhead data signals DOD- to the ERD card.

equivalent bits in the appropriate DPSC, DNAC, and

DNSC inputs to each code comparator. At this time, the

5-503. When parallel sync acquisition is obtained,

three bit error counters are also enabled. During any

signal DSYNC resets the three bit error counters to zero

given minor frame period, the incoming data contain any

and only one of the bit error counters is enabled by signal

one of the three stuff command codes. Therefore, by

PSC enable, NAC en- able, or NSC enable. Starting

the-time word 24 occurs, two of the bit error counters

with bit 0 of word 12 of the incoming data, the selected

are saturated and indicate eight or more errors.

bit comparator compares bit 0 in data words 12 through

23 with the equivalent bits applied in signal DPSC,

DNAC, or DNSC. When proper frame synchronization

5-133