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T.O. 31W2-2GSC24-2
TM 11-5805-688-14-1
NAVELEX 0967-LP-545-3011
5-494. The data outputs from the primary shift register
timing relationships required when both shift registers
for an even number of bits are processed through the A
are used to service a data word containing an odd
and B inputs of the data selector at the system RIO rate.
number of data bits. In this example, the primary shift
After the last programmed data output is processed, the
register that services data words containing 16 data bits
A=B signal from the address comparator is applied as a
is described first, followed by the primary shift register
preset-to-one signal to the 4-bit address counter and as
and odd-bit shift register that service data words
an en- able signal to the odd-bit control circuit. When
containing 17 data bits. In the even-bit mode servicing
LSB signal DPUBO is a 1, representing an odd number
16 data bits, part A in figure 5-38 shows the primary shift
(1, 3, etc), the odd-bit control is inhibited and the C
register waveforms. Note that the R.A.M. write enable
input signal to the data selector is inhibited to program
signal is generated once every two RIO clock times and
the VLSR for operation in the even-bit mode. When LSB
the timing sequence is not altered when the data word bit
signal DPUBO is a 0, representing an even number, the
count is completed and the A=B signal truncates the 4-bit
odd-bit control circuits are enabled when the enable
address counter to start servicing the next data word.
signal is applied from the address comparator. At this
The timing waveforms in part A of figure 5-38 show that
time,  a delay enable signal applied to the write/read
eight write enable signals are generated during one word
delay control circuit inhibits the 4-bit address counter and
time equivalent to 16 data bits. Each write enable writes
the R.A.M. read and write controls for two RIO clock
one pair of SD3 and SD2 bits into the R.A.M. In turn,
times.  This condition effectively delays the first write
eight SD3 and eight SD2 data bits are read out of data
enable input to the R.A.M. for one RIO time. (The write
selector output B1, therefore providing 16 consecutive
enable is normally every other RIO time.)
data bit out- puts for each 16 data bit inputs.
5-497. The waveforms in part B of figure 5-38 represent
5-495. At the same time that the delay enable signal is
the primary and odd- bit shift register in a configuration
generated, the bit enable signal is applied to the odd-bit
that services data words containing 17 data bits. Note
shift register,  one data bit (SD3-) is written into the
that eight write enable signals are still being generated
register,  and the stored data bits in the register are
during one word time for the R.A.M. In turn, 16 data bits
serially clocked one step.  At the same time,  the C
associated with the eight write enable signals are still
select signal enables the B1 and B2 data bits from the
being generated. The half-rate clock output is inhibited
shift register to be routed through the C inputs of the
for one RIO time after the A=B signal is generated. It is
data selector to the code comparator circuits. After the
during this delayed one-half rate clock time that the odd-
two RIO times expire, the inhibits to the 4-bit counter
bit enable clock signal is generated and the odd bit of
and R.A.M. are removed and the even data bit process
data (SD3-) is placed in series with the SD3 and SD2
in the primary shift register is repeated.
data bits. This application provides 17 consecutive data
bit outputs for each 17 data bit inputs in the data selector
5-496.  The preceding paragraphs describe the basic
output.
equipment operation of the primary and odd-bit shift
register circuits. The following discussion illustrates the
5-130

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