Parallel Sync Acquisition Circuits Block

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

In turn, the count decrements one count each time a

Diagram Discussion (Figure 5-36). The input data

count down signal is applied during word 28 when the

pulses (DATA) applied to the data receiver are

counter contains a count between 1 and 5. When the

conditioned into TTL level pulses and applied to the data

counter counts down to zero, the count 0 signal is

flip-flop. In turn, the incoming timing pulses (TM) are

applied to the control circuits. The control circuits, in

conditioned in the timing receiver and applied to the data

turn, remove signal DFS and initiate demultiplexer loss

flip-flop, channel data output shift register, and inverter

of frame signal DLOF that is applied to the ERD card.

U63. Inverter U63 produces the RIO and RIO- system

When signal DFS is removed, the inhibit signal to the

clock signals used in the FS card. The data pulses

parallel sync acquisition circuits is removed and that

clocked through the data flip-flop are applied to the

function is activated to reestablish frame synchronization.

channel data output shift register and to the data shift

5-481. Signal DFS is applied as an en- able signal to the

demultiplexer frame sync signal DFS is applied as an

channel output data shift register while frame

enable signal to the channel data output shift register.

synchronization is maintained. The channel out- put data

This prevents erroneous channel data signals DTI1-

shift register, in turn, generates four identical channel

through DTI4- from being applied to the channel cards.

data outputs (DTI1 through DTI4) that apply the channel

data to each of the de- multiplexer channel cards. When

frame synchronization is lost, the data out- puts are

5-484. Sequential data outputs SD2, SD3, and SD3-

inhibited.

from the data shift register are applied to the VLSR. The

VLSR, which temporarily stores 10 consecutive data

5-482. The PSE and NSE flip-flops pro- duce negative

words to provide a 10-word delay, generates parallel

or positive stuff enable signal DNSE or DPSE to identify

data inputs Bl through B10. The 10 parallel data bits are

the stuff command code contained in the minor frame

applied to three code comparator circuits. The SD3- data

being monitored. When the error count in the positive

output from the data shift register is applied in real time

stuff code bit error counter is less than eight, the PSE

(no delay) as data input Bll to the three code comparator

flip-flop produces signal DPSE during word 28. Signal

circuits at the same time that Bl through B10 are applied

DPSE indicates the presence of a positive stuff

in parallel. The VLSR is clocked by sys- tem clock signal

command that is applied to the ERD and GC/ DM cards.

RIO- so that one set of 10 bits in 10 sequential data

When the error count in the negative stuff code bit error

words is applied to the three comparators at the system

counter is less than eight, the NSE flip-flop produces

clock rate. For example, bit 5 in words 1 through 11, bit

signal DNSE during word 28 to indicate the presence of

6 in words 1 through 11, bit 7 in words 15 through 25,

a negative stuff command. When both counters contain

etc, are each applied during one RIO time to the

error counts of eight or more, both output signals are

comparator circuits.

A separate block diagram

low during word 28 to indicate the presence of a no-

discussion of the VLSR functional circuits is contained in

action stuff command.

paragraphs 5-487 through 5-501.

5-483

Parallel Sync Acquisition Circuits Block

5-125