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T.O. 31W2-2GSC24-2
TM 11-5805-688-14-1
NAVELEX 0967-LP-545-3011
5-485. Each of the three code comparators has a fixed
value between 15 and 31 bits.  To meet the different
11-bit binary code that represents the first 11 bits of one
equipment requirements, the VLSR provides the storage
of the three stuff commands that can be applied to the
locations necessary for the 160 to 320 bits to service the
comparator. The fixed 11-bit code is applied as the B
10 words.  The VLSR has primary and odd- bit shift
input to each comparator and is compared against the Bi
registers that provide the flexible storage requirements
through Bll inputs applied to the A inputs of all three
for the various system applications. The primary shift
comparators.  An A=B output from one of the three
register is a 16 to 32-bit programmable shift register that
comparators is applied to the com- pare enable latches
per- forms a serial-in, parallel-out function. The parallel-
when a compare is made during word 11. A compare is
out function produces in sequential rotation between 16
made when B1 through Bll are bit 0 of overhead words 1
and 32 bits of data, one bit at a time, from the same bit
through 11.
location in each of 10 consecutive words. The odd-bit
shift register provides one bit of data from the same bit
5-486. One of the three compare en- able latches is set
location in each of 10 consecutive words. The primary
to produce signal NAC, NSC, or PSC enable when the
shift register is used when the number of ports in use in
appropriate A=B signal is applied from one of the three
a given system configuration is an odd number of ports
code comparators. The output signal is applied through
(n+1 is even). When the number of ports in use is an
an OR gate and is then clocked through the sync enable
even number of ports (n+1 is odd), both shift registers
flip-flop as frame sync signal DSYNC- for one RIO clock
are used to process the data bits.
period. The appropriate NAC, NSC, or PSC signal is
also applied to one of the three parallel sync latches to
5-488. Figure FO-7 is a simplified block diagram of the
produce the NAC, NSC, or PSC enable signal and the
primary shift register circuits that process the data bits in
parallel sync enable signal.  Once the overall frame
the first two words applied to the VLSR. R.A.M. No. 1
synchronization is established,  signal DFS holds the
and storage register No.  1 basically form the shift
compare enable latch circuits inhibited. When the serial
register circuits that produce selected bits B1- and B2
sync acquisition portion of the sync acquisition function
that represent a given bit in words 1 and 2. R.A.M. No.
performed by the serial compare circuits in the serial
1 is a 64-bit storage device configured for four inputs,
sync acquisition and sync maintenance circuits during
with 16 memory locations associated with each input.
words 12 through 23 is not satisfactory, an error reset
Data bits SD3 and SD2 are clocked in parallel into the
signal from those circuits clears the parallel sync latches
R.A.M. from the data shift register in the parallel sync
and the parallel sync acquisition function is repeated
acquisition circuits. Data bits SD3 (bit 1) and SD2 (bit 2)
during the next minor frame period.
are a pair of consecutive bits of the incoming data
stream applied to the demultiplexer. This pair of data bits
is clocked into inputs DO and D1 once every other RIO-
time, or at a one-half clock rate (RIO/2). Each memory
5-487.
VLSR Concept Discussion.
The VLSR
location is sequentially selected so that 32 data bits can
provides a 10-word delay function so that one data bit in
be clocked into the 32 memory locations associated with
a given bit location in 10 consecutive words can be
inputs DO and D1 during 16 consecutive write enable
sampled in parallel. Therefore, each of the data bits
times. Inputs DO and D1 store the same number of data
sampled is separated from its adjacent bit, in time, by
bits during a given data word scan.
one data word time.  The delay between consecutive
words in a given application is equal to n+l, where n is a
Change 1 5-127

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