BLOCK DIAGRAM DISCUSSION. - TM-11-5805-688-14-10219

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

Therefore, in a no-error condition, a high from U8-8 to

to latch U20. Any low error input to OR gate U23-8

the K input of flip-flop U17-10 causes the output from

causes a card error signal to be generated from inverter

U17 to remain high, indicating a no-error condition to

U28-8 on the positive stuff re- quest (DPSTXX-) line.

OR gate U23-8. Activity detector U22-6 is a retriggerable

multivibrator that is held in conduction until the A=B

5-444. VOICE DECODER (VD) CARD.

signals from U7, that are applied through U11-10, are

missing. When the duty cycle of U22-6 expires, the

5-445. GENERAL. The VD card is a channel option

output goes low and presents an error input to OR gate

card that may be used to service one output channel of

U23-6 in the composite diagnostic logic.

voice data. The VD card function is basically the

complement of the VE card function performed in the

5-442. The functional transition decoder and the data

multiplexer. Functionally, the VD card demultiplexes

output buffer No. 1 circuits are duplicated by the

one channel of digitized voice data out of the high-speed

diagnostic transition detector and data output buffer No.

serial data stream from the far-end multiplexer. These

2 circuits. The du- plicate circuits basically consist of

data are converted from a synchronous digital data

U15, U26-6, U26-9, and U18. The output of diagnostic

format into the original analog (voice) waveforms that

flip-flop U18-9 is the complement of the data bit from flip-

were applied to the multiplexer channel input. The block

flop U1-5 in the functional circuits. The complementary

diagram discussions are based on the block diagram

outputs are applied to exclusive OR gate U13-6, which

shown in figure 5-35. The detailed circuit discussions are

produces a high output in a no-error state. An error

based on the VD card logic diagram in the circuit

condition exists when the in- puts to U13-6 are the same.

diagrams manual.

This causes a low output from U13-6 to be applied to flip-

flop U17-6, which, in turn, clocks a low error signal

5-446. BLOCK DIAGRAM DISCUSSION.

input to OR gate U23-8 in the composite diagnostic logic.

5-447. Functional Circuits.

5-443. Activity detector U22-10 is held in conduction by

the read clock pulses from the APLL circuit. When the

5-448. The incoming digital channel data pulses (DTIX-)

read clock pulses are missing, the duty cycle of U22-10

are clocked serially into a 3-bit shift register by gated

expires and a low-level error signal is applied to OR gate

clock signals DGCXX. The three outputs of the shift

U23-6 in the composite diagnostic logic. Latch U20-6

applies a low-level error signal to OR gate U23-8 in the

looking for a condition wherein all three outputs being

diagnostic composite logic when a high-level error

sampled are either ones or zeros. Three consecutive

condition is generated from transistor Q10 in the data

pulses that are either ones or zeros indicate the

output drivers circuit. A fault in the circuit causes an

presence of high amplitude audio signals or high

unbalanced voltage output from emitter- followers

frequency audio signals encoded in the data message

through Q7 The unbalanced condition forces either Q8

format. Each time three consecutive pulses being

or Q9 into conduction and, in turn, forces Q10 into

sampled are of the same polarity, a boost enable signal

cutoff. When Q10 cuts off, its output goes high and is

is generated and applied to the slope control circuit.

applied through inverter U28-12 as a low-level set input

5-118