Diagnostic Circuits - TM-11-5805-688-14-10218

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

5-439. Each time a clock pulse is applied to U1-5, the

maintain the proper phase relationship between the write

bit applied to the D input from the QO output of U14

and read clock pulses. The clock pulses applied through

causes complementary output signals DATOUT and

switches S4 and S2 are applied to inverter U28-6 and

DATOUT- to be generated. Signals DATOUT and

flip-flop U18-7. The clock pulses applied through inverter

DATOUT- are applied through polarity switch S5 to the

U28-6 are applied to AND gates U24 in the two transition

inputs of amplifiers Q1 and Q2 in the output drivers

decoder circuits. Flip-flop U18-7 produces half- rate

circuit. The function of switch S5 is to change the phase

clock pulses to OR gate U21 in the two transition

relationship of the two data output pulses to meet

decoder circuits. The half-rate clock pulses from the flip-

different system equipment configurations. Transistor

flop are also applied to inverters U19- 6, U28-1, and

is a constant current source for amplifiers Q1 and Q2.

U28-10. The clock pulses through inverters U28-4 and

The amplifiers, in turn, drive push-pull emitter-followers

U28-10 clock the shift registers in the two transition

Q4 through Q7. Setting switch S6 to the balanced (B)

decoder circuits. The clock pulses applied through

position connects break- down diodes VR1 and VR4 (3.3

inverter U19-6 are the read clock pulses that increment

vdc) in parallel with breakdown diodes VR2 and VR3.

the read address counter.

These two breakdown diodes are inserted in the base

circuits of Q4 through Q7 in the balanced output con-

5-441. Diagnostic Circuits. The diagnostic address

figuration to produce +3.0-volt channel data out signals

compare function is initiated when word 24 bit 0 signal

DOXX and DOXX-. In the unbalanced configuration,

DW240X is applied through inverters U6-2 and U6-4 to

switch S6 in the U position disables VR1 and VR4 so that

latch U8. The next read clock pulse from the APLL

VR2 and VR3 produce a +6.0-volt DOXX output signal.

circuit clocks flip- flop U12-9, which, in turn, clocks an

In the unbalanced mode, switch S6 also grounds the

enable signal from flip-flop U12-6 to address comparator

DOXX- output.

U7. At the same time, signal DW240X applied through

inverter U6-2 is also applied to clock the present 4-bit

write address into write latch U10. Signal DW240X is

5-440. APLL Circuit. The count eight output from read

also applied through inverter U6-4 to set the data bit

address counter U2 is the variable input to phase

associated with the 4-bit write address into data latch

comparator U29. The count eight output from write

U11-6. When the read address from U2 applied to the A

address counter U5 is inverted through inverter U6-12

inputs of U7 matches the write address applied to the B

and applied to the reference input of U29. The functional

inputs, the A=B output is produced and applied to flip-

operation of the APLL circuit is the same as that

flop U11-10. The next read clock pulse clocks the Q

described for the APLL circuit in the SB card. There is

output from Ull-9 low and presets flip-flop U12-6 high to

one major exception; only switch S4 is required to set up

inhibit U7. The Q output from U11-10 enables one input

the selected clock bit rate for a given channel

of AND gate U8-8. At the same time, the data bit from

application. Switch S4 has three positions to cover the bit

shift register U14-14 is identical to the data bit out- put

rates of 75, 100, 150, 200, 300, and 400. The three

from flip-flop U11-6. In this circuit configuration, Ull-6 is

switch positions are associated with the Q0, Q1, and

performing a latch function. When both data bits are

Q2 out- puts of counter U27 in the APLL circuit.

identical, the inputs to exclusive OR gate U13-8 are the

Selection of any one of the three switch positions permits

same, thus producing a low inhibit signal to one in- put

clock signals to be generated from the APLL circuit

of AND gate U8-8.

within a frequency range that permits the APLL circuit to

5-117