DETAILED CIRCUIT DISCUSSION - TM-11-5805-688-14-10216

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

detector is a retriggerable multivibrator that is held in

5-431. Diagnostic Circuits. A diagnostic address

conduction by the timing signals. When the output clock-

compare function is initiated when word 24 bit 0 signal

signals are missing,

the multivibrator's duty cycle

DW240X is applied to the address compare control

expires and a low-level error signal is applied to the

circuit, the write address latch, and the data latch. The

composite diagnostic logic. The data output drivers

write address latch stores the 4--bit write address

circuit contains a diagnostic circuit that also produces an

generated at this time. In turn, the data bit associated

error signal to the composite diagnostic logic circuit when

with the 4-bit write address is set into the data latch. The

the circuit malfunctions.

address compare control circuit then generates an

enable signal to the ad- dress comparator.

5-434. The composite diagnostic logic circuit has four

Approximately eight bit times later,

the address

diagnostic error in- puts. When any one of the four

comparator receives a 4-bit address from the read

inputs indicates an error condition, a card error signal is

address counter to its A inputs that is identical to the

generated on the positive stuff request (DPSTXX-) line to

address from the write address latch that is applied to its

the OEG card. When the self-test mode is initiated, self-

B inputs. At this time, the A=B output from the

test signal ST- causes a data no-compare condition to

comparator is applied to the diagnostic flip-flop. When

exist at the data compare logic No. 1 circuits, which, in

the next output clock signal from the APLL circuit is

turn, force the composite diagnostic circuit to generate

applied to the diagnostic flip- flop, a compare enable

signal DPSTXX-. When the DISPLAY RESET switch on

signal from the flip-flop is applied to the data com- pare

the front panel is pressed, error reset signal DERRS- is

logic No. 1 circuit to perform a compare of the data bit

applied to reset the diagnostic circuits to their normal

stored in the data latch against a data bit out of transition

operation. Signal DERRS- is also applied when the

decoder No. 1. Since the two data bits have the same

SELF TEST switch on the front panel is re- leased.

4-bit ad- dress, the data bits are identical in a no-error

condition. Therefore, when the bits are not identical, an

5-435. DETAILED CIRCUIT DISCUSSION.

error signal is developed and applied to the composite

diagnostic logic.

5-436. Input-Output Buffer Function. The incoming

5-432.

Diagnostic transition decoder No.

2 and

channel data pulses (DTIX-) are clocked through data

diagnostic data output buffer No. 2 duplicate the function

input buffer U1-8 and are applied serially to data elastic

performed by transition decoder No. 1 and data output

storage register U3, U4. The data are clocked through

buffer No. 1. The diagnostic circuits generate a series

the buffer and into the storage register by gated clock

of output data bits that are the complement of the data

signals DGCXX. The gated clocks increment write

bits out of the functional circuits. When the two data bits

address counter U5, which, in turn, produces the

are not complementary, the data compare logic No. 2

sequential 4-bit write addresses that are applied to the

circuit generates an error input to the composite

data elastic storage register. The 4- bit read addresses

diagnostic logic circuit.

that select the locations from which the data are read out

are produced by read address counter U2.

5-433. The output clock- timing signals from the APLL

circuit are monitored by the timing activity detector. The

5-115