DETAILED CIRCUIT DISCUSSION-CONT. - TM-11-5805-688-14-10198

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

5-369. System clock signal Ro from the reference timer

+ 2 bits signal EOS2 for U18-6 in the word 24 detector

card is applied through a series of inverters (U20 and

circuit. Signal EOS2 is also clocked through U18-9 to

U24) to produce system clock signals MRIO and

produce end-of-scan +3 bits signal EOS3. Signal EOS3

MRIO1through MRI08-.

Retriggerable one-shot

from flip-flop U18-9 is buffered through the three U19

multivibrator U12-10 in the system clock activity detector

inverters and inverter U22 to produce end-of-scan 3

circuit is held in conduction by signal Ro. When Ro is

signals MEOS3Nl through MEOS3N4 for the channel

missing, the one-shot multivibrator's duty cycle expires

cards.

and its output sets latch U7, which, in turn, generates

loss of timing signal DLOT- that is applied to the display

5-372. Setting the SELF TEST switch on the front panel

card. The latch remains set until reset signal ERST is

to the on (up) position applies self-test signal ST2to the

applied when the DISPLAY RESET switch on the front

card. Signal ST2- inhibits retriggerable multivibrator

panel is pressed.

U12-7 in the word 24 activity detector circuit, which sets

latch U13 so that a high level error signal is applied to

5-370. When word count 23 is applied to AND gate U16-

AND gate U9-8 in the composite error detector circuit.

6 by word count signals MWC0, MWC1, MWC2, and

Retriggerable multivibrator U12-10 in the system clock

MWC4, and end-of-scan signal EOS2 from U23-5 is

activity detector circuit is also inhibited by ST2- so that

applied to clock flip-flop U18-6, the word 24 signal is

latch U7 is set to produce diagnostic loss of timing error

generated.

The word 24 signal is buffered and

signal DLOT-. In the self test mode, during word 24, all

distributed through inverters U14 and U19 as word 24

the active inputs to the four multiplexers are low. Signal

signals MW24N1through MW24N4- to the channel

ST2- is applied through the three U11 inverters and the

cards. The output from U18-6 is also applied to AND

OFF positions of DIAGNOSTICS AND OVERHEAD

gate U21-11, which, in turn, produces signal M24EOS2

switch S1 to place a low level signal on each of the

when end-of-scan signal EOS2 is applied at its other

unused inputs of the two positive stuff multiplexers. This

input from flip-flop U23-5 during word 24. AND gate U16-

configuration ensures a continuous high input to each of

8 also produces a word 24 output when the word 24

the four exclusive OR gates (U8) in the comparator

output from U18-6, EOS3 from U18-7, and Ro are

circuit. Signal ST2- places a high-level signal to one

present. The pulsed output from AND gate U16-8 is

input of exclusive OR gates U8-3 and U8-11. The result

applied to the four U22 inverters to produce word 24 bit 0

is a high-level error signal from J-K flip-flop U15-7 in the

signals MW2401through MW2404-. These signals are

comparator circuit to AND gate U9-8 in the composite

also routed to the channel cards.

error detector circuit. The three high-level inputs to AND

gate U9 result in the generation of low-level OEG card

5-371. End-of-scan signal MEOS is clocked through two

diagnostic signal MTMOG from OR gate U13-4 in the

stages of flip-flop U23 by R to generate end-of-scan

composite error detector circuit. Reset signal ERST is

applied to the card when the SELF TEST switch on the

front panel is set to the off (down) position or the

DISPLAY RESET switch on the front panel is pressed.

Signal ERST resets the two diagnostic latch circuits (U7

and U13) and forces J-K flip-flop U15-7 to reset and

return the diagnostic circuits to their functional no-error

state, assuming that there are no malfunctions on the

card.

5-97