REFERENCE TIMER (RT) CARD

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

Ro selected is a binary quotient of the source frequency.

5-373. REFERENCE TIMER (RT) CARD.

Signal Ro through S6 is applied to the system clock

buffer and to the phase-adjust circuit. The Ro output

5-374. GENERAL. The reference timer card is one of

from the buffer is applied to the data retiming flip-flop,

the common cards used in the multiplexer. The card

system clock activity detector and to the OEG card. The

generates system clock signal Ro that is applied to the

phase adjust circuit contains a factory adjustment (S3)

OEG card, which, in turn, duplicates and distributes the

that phases the timing output signals (TIMOUT and

master clock signal as multiplexer clock signal MRIO to

TIMOUT-) to the serial digital data outputs (SDATAO and

the multiplexer cards. The card accepts the multiplexed

SDATAO-). The data and timing output signals from the

serial digital data (MSD) from the GC/DM card, develops

line switches can be applied to a balanced or unbalanced

the multiplexer timing out signal TIMOUT, and clocks the

line.

When the system is used in a balanced

associated timing data and timing pulses from the card

configuration, the output data and timing line switches

at the selected Ro rate. Timing signals T3600 and

are set so that the two data signals and the two timing

T4800, generated on the card, are routed to the

signals are applied to balanced lines. When the system

transition encoder cards in the multiplexer. The block

is used in an unbalanced configuration, the output data

diagram for the circuits described below are shown in

and timing line switches are set so that the SDATAO and

figures 5-28 and 5-29. The logic diagram associated with

TIMOUT-signal outputs are inhibited by connecting their

the detailed circuit discussion is contained in the circuit

output pins to ground.

diagrams manual.

5-377. The timing error detectors monitor the TIMOUT

5-375. BLOCK DIAGRAM DISCUSSION.

and TIMOUT-output voltages, and detectors generate a

diagnostic error signal to the composite OR gate and

5-376. System clock signal Ro is developed from

latch circuits when a malfunction is detected. The

external multiplexer timing signals (TIMIN) that are

composite OR gate and latch circuits also have error

applied to the line receiver circuits (figure 5-28) or from a

signal inputs from the 3600Hz and 4800-Hz activity

master oscillator on the card. The input to be used for

detectors in the transition encoder timing circuits on the

developing Ro selected by strapping switch S5 to its INT

card. The five diagnostic error inputs are ORed together,

or EXT position. The signals through S5 are applied to

and when any one of the inputs contains an error

the 15-stage binary counter and to the loss-of-timing

condition, the error signal sets the latch circuit to

activity detector. Switch S6 is strapped to position 1

generate reference timer diagnostic signal MRT that is

(output of S5) when the selected Ro is the same

applied to the display card. The loss of-timing activity

frequency as the source frequency. The switch is

detector error output is set when the timing signal

strapped to one of the positions 2 through 16 when the

through S5 is missing. Reset signal ERST resets the

error detection circuits back to their no-error state when

the DISPLAY RESET switch on the front panel is

pressed.

Diagnostic signals MLOT and MRT are

produced to represent error conditions when the SELF

TEST switch on the front panel is set to the on (up)

position and self test signal ST2is applied to the error

detection circuits.

5-98