Diagnostic Function - TM-11-5805-688-14-10193

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

For a no action condition, neither signal MPSA nor

reverse binary code read out of US0 during bit 0 of words

MNSA is generated. Therefore, signals MNSE and

24 through 28 identifies the used port being serviced

MPSE are not generated and signals PSE and NSE are

during the minor frame identified in the frame count

high-level inputs to the C input of address selector U43.

signals at the output of counter US, U6. For example,

minor frame 3 (count 00011 from U5, U6) services port

5-346.

The absence of word count signal

24 (count 11000 from U50).

WC2429enables the B input of U43 during words 1

through 23. During words 1 through 23, one 3-bit stuff

5-348. Diagnostic Function.

command code is applied through U43 to the data select

inputs of overhead data multiplexer U50. The 2-bit stuff

5-349. Composite Error Detection Circuit. A low-level

code enables the data inputs at pin 6, 7, or 9 so that the

input to any one of the three inputs to OR gate U12-8

appropriate stuff code (NAC, NSC or PSC) is routed

places a high-level signal to the input of error flip-flop U2.

through multiplexer USO0 to input IO of output data

The flip-flop, in turn, produces data mux diagnostic error

multiplexer U57. The 3-bit binary stuff command codes

signal MDM- when the next multiplexer clock signal

that can be applied during words 1 through 23 are shown

MRIO- clocks the flip-flop. Two of the inputs to OR gate

below.

U12 are provided from word 29 activity detector U1-10

and from minor frame activity detector U1-6. Both

5-347. Word count signal WC2429enables the B input of

activity detectors are retriggerable multivibrators that are

U43 during words 24 through 29. Five sequential binary

held in conduction by the word 29 signals (MW29) or

addresses derived from word count signals WC0, WC1,

minor frame signals (MFC1).

When the signal is

and WC2 are applied through the B input of U43 to the

missing, the stage will complete its duty cycle and

data select inputs of overhead data multiplexer U50.

produce a low-level error signal to OR gate U12. The

The WCO, WC1, and WC2 codes applied during words

third input to OR gate U12 is from exclusive OR gate

24 to 29 are 000 (enables pin 1 on U50) through 101

U23-6, which samples signal MSD from the functional

(enables pin 5 on U50). Minor frame count signals

data multiplexer circuit and diagnostic signal MSD from

MFCO through MFC4 from minor frame counter U5, U6

the diagnostic equivalent circuits. When a malfunction

are applied in reverse order to input pins 1 through 5 of

occurs, signals MSD and MSD- will eventually compare

U50. The most significant digit (signal MFC4) is applied

and cause the exclusive OR gate to generate a low-level

to pin 1 (first bit sampled), and the least significant digit

error signal to OR gate U12.

(signal MFCO) is applied to pin 5 (last bit sampled). The

3-Bit Address Code

Signal to Latch U42

to U50 From U43

Stuff Input to U50

MPSA (positive stuff)

Pin 6 (PSC)

MNSA (negative stuff)

Pin 7 (NSC)

Neither (no action)

Pin 9 (NAC)

5-92