Data Multiplexer Function - TM-11-5805-688-14-10192

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

During word 29, the comparator is enabled and output

and one bit from each of the channel data inputs

signal A=B is produced when the incoming channel

(MDT001 through MDT015) applied from the active

address matches the overhead channel address applied

channel cards. The single serial data stream from

to the B input of the comparator. Signal A=B and signal

multiplexer U57 is applied through inverter U13-12 to

MNSE are applied to AND gate U24-12. The output from

reclocking flip-flop U22. Complementary serial data

flip-flop U25 to AND gate U24 is high for one multiplexer

streams MSD and MSD are clocked out of U22 at the

clock time (MRIO). AND gate U24, in turn, generates an

multipliexer clock MRIO rate. Signal MSD is routed to

inhibit to AND gate U16-11 for one clock time. This

the reference timer card and signal MSD is applied to the

condition causes a high-level inhibit signal to 1-of-16

composite error detection function.

decoder U51, U52, preventing one gated clock signal

from being generated for the designated channel

5-345. Overhead data multiplexer U50 combines the

address. Flip-flop U25 is configured so that only one

overhead data inputs for a selected port into the serial

signal A=B can enable AND gate U24-12 in word 29 of a

overhead data format that is applied to one input of

minor frame. Otherwise, other used ports strapped to

output data multiplexer U57 during bit 0 of words 1

the selected active channel could also develop a

through 28 in each minor frame period. The serial

negative stuff condition when the redundant channel

overhead data contains one of the three stuff command

address appears and is compared with the channel

signals (PSC, NSC, and NAC) in bit 0 of words 1

address applied to the B input of channel address

through 23 of each minor frame. Bit 0 of words 24

comparator U47.

through 28 of each minor frame contains the 5-bit binary

code for the port receiving overhead service during a

given minor frame. Positive stuff command signal MPSA

5-343. Data Multiplexer Function.

and negative stuff command signal MNSA from the OEG

card are applied through three AND gates U34 to

5-344. Output data multiplexer U57 combines up to 15

positive stuff latch U42-10 and negative stuff latch U42-

channels of output data (MDT001 through MDT015) from

6. At the end of each minor frame, the selected stuff

the active channels in the multiplexer, together with one

command is clocked into the appropriate latch by minor

overhead data channel input from overhead data

frame transition signal MFT from AND gate U4-3. When

multiplexer U50. Channel addresses GCAD1 through

a positive stuff condition is initiated, latch U42-9

GCAD8 from address selector U53 sequentially select

produces signal MPSE, which is applied to U12-6 (pin 70

the data inputs to output data multiplexer U57. Channel

strapped to pin 89) in the gated clock generation circuits,

addresses GCAD1 through GCAD8 are routed through

and U49-10 produces signal PSE-, which is applied to

delay registers No. 1, No. 2, and No. 3 (U49, U55, and

the C input of address selector U43. Initiation of a

U56) to the multiplexer. The three registers provide a

negative stuff generates signal MNSE from latch U42-7,

time delay that is equal to three multiplexer clocks

which is applied to U24-12 (pin 29 strapped to pin 87) in

(MRIO) to compensate for the time delay in the data TTL

the gated clock generation circuits, and U42-6 produces

circuit applications. The channel addresses applied from

signal NSE-, which is applied to the C input of address

U56 to data output multiplexer U57 sequentially select

selector U43.

one overhead data bit from overhead multiplexer U50

5-91