Gated Clock Generation Function - TM-11-5805-688-14-10191

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

In this state, the applied channel address signals are

a negative stuff condition, or neither signal to indicate a

routed directly through U53 to the inputs of 1-of-16

no-action condition. When a channel address is applied

decoder U51, U52. The l-of-16 decoder contains two 1-

to the GC/DM card during a minor frame period

of8 decoders that decode the four-bit channel address

associated with an unused port, signal MMF=PS is not

into the appropriate gated clock signal (MGCO1 through

generated, and the channel address from overhead

MGC15) representing the selected channel address. In

this normal operating configuration, one gated clock

the OEG card is an inactive channel; therefore, a no

signal is generated for each channel address clocked

action condition is reflected back to the GC/DM card.

into the circuits.

Signal MPSE or signal MNSE is never applied to the

GC/DM card in response to channel address 0000. The

5-339. overhead service for a given channel address is

channel address in overhead register No. 1 is clocked

initiated when minor frame equals port sequence signal

into overhead register No. 2 (U54) by minor frame

MMF=PS is applied to U18-5 in the register control

transition signal MFT. Signal MFT is generated from

circuit. Signal MMF=PS from the sequencer card is only

AND gate U4-3 when signals MEOS2B and MW29 are

applied to U18-5 during word 28 of each minor frame

applied to the AND gate. The channel address clocked

that services a used port. During word 27, signal W27

into overhead register No. 2 is applied to the B input of

and end-of-scan signal MEOS2B initiate the master reset

channel address comparator U47 and to the B input of

signal from AND gate U19-3 in the register control circuit.

address selector U53.

The master reset signal, in turn, resets the output from

overhead register No. 1 (U48) to 0000 in word 27 of

5-341. When a positive stuff action is designated for the

each minor frame period. The output from U48 remains

channel address being interrogated on the OEG card,

0000 during each minor frame period not assigned to

signal MPSE is applied to U12-6 in the gated clock add

service a used port.

When signal MMF=PS is

control circuit. Signal MPSE, together with signals

generated, a load signal is applied to overhead register

MEOS2B and word 28 (from flip-flop U3-5) enable AND

No. 1, and the channel address (MCHADO through

gate U12-6 so that flip-flop U11, in turn, generates the B

MCHAD8) applied to the card is loaded into overhead

enable signal to address selector U53. The B enable

signal enables the B input of U53 so that overhead

address stored in overhead register No. 2 (U54) is

5-340. The output from overhead register No. 1 (U48) is

applied to 1-of-16 decoder U51, U52. The 1-of-16

applied to overhead register No. 2 (U54) and to the OEG

decoder, in turn, generates one additional gated clock

card as overhead address count signals MOHO through

signal during bit 0 of word 29 for the active channel

MOH3. The channel overhead address count signals

address designated for the positive stuff bit.

interrogate the OEG card to see if the selected channel

is requesting one of the three overhead service

5-342. When a negative stuff action is designated for

conditions: positive stuff, negative stuff, or no action.

the channel address being interrogated on the OEG

The OEG card, in turn, applies signal MPSE for a

card, signal MNSE is applied to AND gate U24-12 in the

positive

stuff

condition,

signal

MNSE

for

gated clock delete control circuit. When signal MFT

occurs, the channel address being interrogated on the

OEG card is applied through overhead register No. 2

(U54) to the B input of channel address comparator U47.

5-90