OVERHEAD ENABLE GENERATOR OEG CARD

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

5-350. Gated Clock Error Generation Circuit. The gated

5-354. In the multiplexer, the OEG card performs three

clock error generation circuit consists of four 8input

functions. First, the OEG card accepts positive and

comparators U45, U38, U46, and U39 that provide four

negative stuffing requests from the active channel cards

A=B outputs to AND gate U9-8, which, in turn, provides a

and then multiplexes the positive stuffing requests into

signal to the input of gated clock error flip-flop U2. When

one positive stuff acknowledge output stream, and the

the 15 gated clock outputs (MGCO1 through MGC15)

negative stuff requests into one negative stuff

from function 1-of-16 decoder U51, U52 compare with

acknowledge output stream. The two serial output

the gated clocks from the diagnostic 1-of-16 decoder

streams are routed to the GC/DM card for overhead

U30, U31, four high-level signals A=B hold AND gate U9-

servicing. During word 24 the positive stuff acknowledge

8 in conduction so that a low-level signal is applied to the

stream contains the diagnostic status for the channel

input of flip-flop U2. When one or more of the functional

cards. This data is routed to the display card as part of

gated clocks in one of the comparators do not compare

the diagnostic function during word 24. Second, system

clock signal R0 from the reference timer card is applied to

with the diagnostic gated clocks, the A=B output goes

the OEG card, which then redistributes the signal as

low and inhibits AND gate U9. In turn, AND gate U9

multiplexer system clock signals MRIO1through MRI08to

places a high to the input of flip-flop U2 so that gated

other cards in the multiplexer. Third, the OEG card

clock error signal MGC is produced the next time signal

generates word 24, word 24 end of scan 2, word 24 bit

MRI0-clocks the flip flop. Both error flip-flops U2-6 and

0, and end-of-scan (EOS) signals by decoding signals

U2-7 can be set to the self-test state by self-test signal

from the word counter and end-of-scan logic. The signals

ST2and can then be reset by signal ERST.

are then routed to the channel cards and to the display

card for timing purposes.

5-351.

OVERHEAD ENABLE GENERATOR OEG

CARD.

5-355. In the demultiplexer, the negative stuff request

circuits are not used on the OEG card. The positive stuff

5-352. GENERAL.

request lines are used only for the diagnostic data

required for the diagnostic function on the display card.

5-353. The OEG card is one of the common cards. Two

OEG cards are used in the multiplexer set: one in the

5-356. BLOCK DIAGRAM DISCUSSION.

multiplexer and one in the demultiplexer. The block

diagram for the circuits described in the block diagram

5-357. In the multiplexer, positive stuff request signals

discussion is shown in figure 5-27. The logic diagram

MPST01through MPST15from the channel cards are

associated with the detailed circuit discussions is

applied through the ON positions of the DIAGNOSTICS

contained

the

circuit

diagrams

manual.

AND OVERHEAD switches to positive stuff multiplexer

No. 1 Negative stuff request signals MNST01through

MNST15are applied to negative stuff multiplexer No. 1.

5-93