Gated Clock Generation Function - TM-11-5805-688-14-10183

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

normally receive four gated clock signals MGCO1. The

clock signal (MGC01 through MGC15) that is routed to

port-to-channel assignment is programmed and

the designated channel card.

performed on the sequencer (seq) card. The seq card,

in turn, applies the appropriate channel assignment for

5-319. An overhead service function is initiated when

each used port back to the GC/DM card through 4-bit

minor frame equals port sequence signal MMF=PS

binary channel address signals MCHAD1 through

selects the channel address associated with the used

MCHAD8. Since a maximum of 15 active channels can

port that has access to overhead service during a given

be used, gated clock signals from the GC/DM card are

minor frame period. One signal MMF=PS is applied one

designated as MGC01 (channel 1) through MGC15

time to the register control circuit for each used (active

(channel 15).

and strapped) port associated with each channel

address during one major frame period. Before signal

5-317. In addition to the normal gated clock signals that

MMF=PS is applied to the card from the sequencer card,

are generated as described in paragraph 5-316, each

MEOS2B and word 27 signal W27 enable the register

used port receives overhead servicing during a

control circuit to generate a reset signal to overhead

designated minor frame in each major frame period.

During word 29 of the minor frame designated for a

particular port, the total number of gated clock signals

signal MMF=PS is present to identify a minor frame that

applied to the active channel with which the port is

services a used port. Therefore, the output is 0000 for

associated may be increased or decreased by one, or

each minor frame period associated with an unused port.

left unchanged. If a gated clock signal is deleted, it is the

The 0000 channel address prevents unused ports from

first gated clock signal normally routed to that channel

gaining access to overhead service as described in the

during word 29. If an extra gated clock is added, it is

detailed theory of operation. Signal MMF=PS enables

generated and applied to the channel during bit 0 of word

the register control circuit to generate a load signal to

29.

overhead register No. 1 during word 28. The load signal,

in turn, loads the present channel address (MCHADO

5-318. In normal operation, 4-bit binary channel address

through MCHADB) into overhead register No. 1. This is

code MCHAD1 through MCHAD8, from the sequencer

the channel address for the active channel that receives

card, selects the channel number of the channel card

overhead service during the next minor frame period. At

that will receive a gated clock signal. The channel

the end of each minor frame, minor frame transition

address is routed to the channel address comparator,

signal MFT enables overhead register No. 2 to load the

overhead register No. 1, and the address selector. In

channel address in the output of overhead register No. 1.

normal operation, the channel address for the channel

At this time, the address loaded into overhead register

that receives the next gated clock is routed directly to the

No. 2 is applied to the B input of the channel address

C input of the address selector. The C input is enabled

comparator and to the address selector. The channel

by the C enable signal from the gated clock add control.

address loaded into register No. 2 is also applied as

The address in the address selector is applied to the 1-

overhead address count signals MOHO through MOH3

of-16 decoder and is decoded into the appropriate gated

the

OEG

card.

5-82