Data Multiplexer Function - TM-11-5805-688-14-10184

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

5-320. The channel address applied to the B input of

5-323. The data multiplexer functional circuits interleave

the channel address comparator identifies the channel

up to 15 channel data inputs from the channel cards,

selected for overhead servicing. When the incoming

plus the overhead data input, into one serial digital data

channel address applied to the A input of the channel

stream that is routed to the reference timer card. The 4-

address comparator during word time 29 matches the

bit binary channel addresses (GCAD1 through GCAD8)

address at the B input, signal A=B is generated and

select the inputs applied to the output data multiplexer.

applied to the gated clock delete control circuit. The

The signals are routed through three delay registers to

gated clock delete control circuit, in turn, generates an

provide an accumulated time delay of three MRIO time

inhibit signal to the 1-of-16 decoder when A=B and

periods and compensate for the time delay in the logic

negative stuff enable signal MNSE are applied to it. The

implementation that is required to apply a gated clock to

inhibit signal applied to the l-of-16 decoder prevents the

a channel card, interrogate the channel for data, and

circuit from decoding and generating a gated clock signal

then transmit the data back to the output data

for the channel address being applied to it. Thus, one

multiplexer. Each 4-bit channel address selects one of

normal gated clock signal is deleted from the designated

the channel data inputs or the overhead data input that is

channel address during word 29 for a negative stuff

applied to the output data multiplexer. Channel data out

overhead function.

signals MDT001 through MDT015 are the maximum

number of inputs that can be routed from the channel

5-321. When positive stuff enable signal MPSE and

cards to the output data multiplexer. Only those signals

end-of-scan signal EOS2B are applied to the gated clock

representing the active channels are actually applied to

add control circuit during word 28, a B enable signal is

the output data multiplexer. For example, a system with

generated and applied to the address selector. The B

six active channels applies signals MDT001 through

enable signal to the address selector routes the channel

MDT006. Once each word time, an overhead bit is

address at the B input to the l-of-16 decoder. The 1of-16

routed from the overhead data multiplexer to the output

decoder, in turn, decodes and generates a gated clock

data multiplexer. During each word time, one data bit

signal for the selected channel address. Thus, one

representing each strapped port associated with the

additional gated clock signal is generated during bit 0 of

active channels is applied to the output data multiplexer.

word 29 in the performance of the positive stuff overhead

Under control of channel address signals GCAD1

function. The channel address routed through the

through GCAD8, the inputs to the output data multiplexer

address selector is also applied as 4-bit binary channel

are interleaved into a serial data stream that is applied to

address signals GCAD1 through GCAD8 to the data

a reclocking flip-flop circuit. The flip-flop circuit, in turn,

multiplexer function to select the channel data inputs to

produces complementary output serial data streams

the multiplexer for the active channel cards.

MSD and MSD that are clocked by multiplexer clock

MRIO. Output serial data stream MSD, which is the

multiplexer output signal, is routed to the reference timer

5-322.

Data Multiplexer Function (Figure 5-24).

card, and MSD- is applied to the frame sync for loopback

test purposes.

5-83