Input-Output Data Buffer Function

T.O. 31W-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

16-port register that has the capability for data bits to be

load enable signal is applied from the initialization logic to

written into the register at the same time that stored data

the rate compare control. With the load enable signal

are read out (at a different address). The write address

applied, the control generates a load signal when the

counter, which is sequentially incremented by the

next timing signal from the timing receiver is applied.

conditioned channel timing pulses, generates the 4-bit

The load signal causes the write address latch to load in

write addresses that are applied to the elastic storage

the write address from the write address counter. The

load and load enable signals from the initialization circuit

counter is sequentially incremented by the gated clock

are inhibited if a reset signal is applied from OR gate

(GCXX) pulses applied through switch S3. Switch S3

U47. The addresses in the two latches are applied to the

selects the mode of operation as described in the

B-C-1 adder, where the write address count is subtracted

simplified block diagram discussion.

In the RCB

from the read address count to provide a 4-bit count to

position, the incoming gated clocks (GCXX) from the

the decoder logic. The decoder logic, in turn, decodes

GC/DM card are routed directly to the read address

the adder output to determine if a stuffing action is

counter. In the URC position, the gated clocks are

required, an out-of-tolerance condition exists, or no

routed through the coarse rate conversion circuits, where

action is required. The decoder logic is configured so

the gated clock bit rate is modified as described in the

that, during a rate compare, the offset between the write

simplified block diagram discussion. The read address

and read address is a predetermined count. Should the

counter generates the read addresses that are applied to

offset between the write address and the read address

a holding register, and the read address latch. The read

become greater than the predetermined count, a positive

addresses are clocked out of the holding register to the

stuff (POS) command is decoded. If the offset between

elastic storage register by the multiplexer master clock

the write address and the read address is less than the

signal MRIOX-. The serial data out of the elastic storage

predetermined count, a negative (NEG) stuff command

is decoded. When the offset variation between the

system clock signal MRIOX-. The data in the buffer are

addresses is greater than the compensatory capability of

sampled at a selected time by the GC/DM card.

the buffer function, an out-of-tolerance (OOT) command

is decoded. When the read address is effectively

5-177. Input-Output Data Rate Compare Function. The

tracking the write address (within tolerance), none of the

channel data and associated timing applied to the RCB

three above commands are generated to indicate a no-

card are asynchronous to the multiplexer timing and can

action condition.

vary +250 ppm from the multiplexer's nominal data rate.

Any variation of the applied data rate with respect to the

5-178. An out-of-tolerance (OOT) signal from the

multiplexer's data rate is detected and compensation is

decoder logic generates a reset signal to the initialization

initiated by this function. A rate compare is initiated

circuit. When a reset signal is applied to the initialization

when a read address is loaded into the read address

circuit, the circuit generates a reset signal to the read

latch by the load signal applied from the initialization logic

address counter that resets the counter to a count of 0.

to the latch during word 24 bit 0. At the same time, a

The initialization logic also generates a preset

Change 1 5-42