Input-Output Data Buffer Function-CONT.

T.O. 31W-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

signal, two clock times later, to the write address

count during each word until the end-of-scan signal in

counter that presets the counter to a count of 10. The

word 24 of minor frame count 31 occurs. At this time,

preset and reset signals are generated from the

the word counter preset control generates a preset signal

initialization logic during word 24. The offset in count

that presets the word counter binary output to zero.

(normally a count of 8) between the two counters

End-of-scan signal MEOS3NX, together with word 24

prevents them from generating identical read and write

MW24NX-, clocks a data bit into the 5-bit shift register

addresses to the elastic storage register at the same

so that an inhibit signal is clocked out from the register

time. The OOT signal is also applied to the stuff

during word 29. The inhibit signal during word 29 inhibits

comparator as described below.

the word counter and the gated clock control so that a

gated clock cannot be deleted during word 29. Word 29

5-179. A negative stuff (NEG) signal from the decoder

is used for the normal overhead service function. Each

logic is applied to the stuff comparator, and the signal is

word count from the word counter is applied as the A

also routed as signal MNSTXX to the OEG card. The

input to the 10-bit comparator. Before the circuits are

positive stuff (POS) signal from the decoder logic is also

activated, 10 fill-bit strapping switches (O through 9) are

applied to the stuff comparator and is processed to the

strapped to a predetermined count that is related to the

OEG card as described in the diagnostic function

number of gated clocks to be deleted during a major

discussion.

frame. The 10-bit binary code from the strapping

switches is applied as the

B input to the 10-bit

5-180. The stuff comparator performs a comparison of

comparator.

The 10-bit comparator continually

the three outputs from the decoder logic circuits in the

compares the 10-bit binary code (A) from the word

functional circuits with the three out puts from the

counter with the programmed 10-bit binary code applied

decoder logic circuits in the diagnostic circuits. The

from the fill-bit strapping switches. Each time that a

three outputs from the diagnostic circuits should be

binary code applied as the A input is greater than the

duplicates of the three out puts in the functional circuit.

programmed B input, the gated clock inhibit signal is

Therefore, when the outputs do not compare, the A is not

generated and applied to the gated clock control logic. In

equal to B signal is applied from the stuff comparator to

a straight binary code comparison, the gated clocks to be

OR gate U47. OR gate U47, in turn, generates a reset

deleted when A is greater than B would be grouped,

signal to the initialization logic that resets the read and

thus causing deletion of an undesirable series of

write address counters as previously described. The

consecutive gated clocks. To prevent this condition, the

stuff comparator also performs diagnostic functions as

outputs from the word counter are reversed so that the

described in the diagnostic circuits description.

MSB of the counter is applied to the LSB of the A input

to the 10-bit comparator. As a result, a homogeneous

5-181. The coarse rate conversion circuits (figure 5-13)

spread of the gated clock deletions is obtained by the

produce modified gated clocks to the read address

reversed binary count function.

counter when switch S3 is set to the URC position. In

normal operation, end-of-scan signal MEOS3NX

5-182. Detailed Diagnostic Block Diagram Discussion

increments the word counter to generate a 10-bit binary

(Figure 5-14).

code

that

sequentially

advances

one

5-43