DEMULTIPLEXER BASIC CONCEPTS

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

address to the OEG card, the negative stuff request

demultiplexer transmission link may be subject to data

signal is applied back to the GC/DM card. As a result,

errors induced by atmospheric fading, lightning hits, or

one normal gated clock signal GC03 is deleted during

other such phenomena.

word 29 in one preselected minor frame.

5-59. Frame acquisition and maintenance by the

5-54. Each additional gated clock signal generated as

demultiplexer is accomplished by the use of the 23-bit

a result of a positive stuff request occurs during bit 0 in a

stuff code pattern inserted in the overhead word of the

given word as shown in D of figure 5-6. Each gated

multiplexer's output (paragraph 5-13). As discussed in

clock that is deleted as a result of a negative stuff

paragraph 5-13, each minor frame transmitted by the

request occurs in the first bit time assigned to the given

multiplexer contains one of three stuffing codes in the

channel as shown in E of figure 5-6. In a no-action

first 23 bit positions of the 29-bit overhead word. The

condition, the channel continues to receive one gated

demultiplexer is designed to recognize any of the three

clock in each word period for each used port assigned to

codes and to synchronize its timing circuits with the

the channel.

received code. Within prescribed limits, received codes

may contain errors not present when the code was

5-55.

DEMULTIPLEXER BASIC CONCEPTS

transmitted by the multiplexer.

5-56. Two functions are considered unique to the

5-60. The demultiplexer frame synchronization circuits

AN/GSC-24(V) demultiplexer.

One is the frame

operate in two modes: frame acquisition and frame

synchronization

function,

which

enables

the

maintenance. When the demultiplexer first receives data

demultiplexer to acquire and maintain frame

from the transmitting multiplexer, the frame acquisition

synchronization with the transmitting multiplexer. Such

mode is automatically selected. Once initial frame

synchronization is accomplished in relatively severe error

acquisition is accomplished within prescribed error

environments. The second function is commonly termed

limitations, the frame synchronization circuits switch to a

smoothing, and is associated with the demultiplexer's

frame maintenance mode. The circuits remain in this

ability to compensate for stuffing operations performed

mode until the number of received errors exceeds a

by the multiplexer without inducing unacceptable

second set of prescribed limits or until the demultiplexer

perturbations in the demultiplexer channel timing

data input is otherwise interrupted. Figure 5-8 depicts a

outputs. The frame synchronization and smoothing

simplified block diagram of the demultiplexer frame

functions are conceptually introduced in paragraphs 5-57

synchronization function.

through 5-67.

5-61. In the frame acquisition mode, serial data

5-57. FRAME SYNCHRONIZATION FUNCTION.

entering the demultiplexer are routed to a variable length

shift register (VLSR) whose length is controlled by port

5-58. The demultiplexer uses a frame synchronization

strapping assignments in the demultiplexer common

technique that enables acquisition and maintenance of

electronics section. The varying of shift register length is

frame synchronization in the presence of errors in the

set to correspond to the variable length data word

received synchronization pattern. Such an arrangement

transmitted by

ensures a high degree of bit count integrity in situations

where

the

multiplexer-to

Change 1 5-16