CHANNEL DATA GATING FUNCTION.

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

rate (Rc ) of 288 kbps requires the use of three used

in a multiplexer for processing of channel inputs not

ports (K) when gated clock signals occur at a port

synchronized with internal multiplexer timing signals.

sampling rate (Rp) of 96 kbps.

Regardless of their input form (digital with timing, voice,

or digital without timing), all channel data inputs are

5-46. During each data word period, each used port in

processed by the appropriate channel card type, so that

the multiplexer normally receives one gated clock signal.

the output from each channel card is in a digital form that

Therefore, if a channel has four used ports, that channel

is synchronous with the timing of the multiplexer's

normally receives four gated clock signals during a word

common electronics section.

period. The gated clock signals applied to one multiport

channel are not applied sequentially or in a group, but

5-42.

CHANNEL DATA GATING FUNCTION.

rather are applied in a near-homogeneous sequence as

5-43. Each active digital channel in a multiplexer is

shown in figure 5-5. In figure 5-5, under the "ACTIVE

configured so that, over a given period of time, the bit

CHANNEL SAMPLING SEQUENCE" column, each entry

rate at which the data bits are read out of a channel card

indicates the channel card that receives one gated clock

is equal to the channel data bit rate at which the data bits

during the bit time (per word time) listed under the "BIT

are written into the channel card from an external source.

SAMPLING SEQUENCE" column. Note that channel

Since the data inputs are asynchronous to the

No. 1 has three used ports and receives a gated clock

multiplexer internal timing functions, data cannot be

signal during bits 5, 9, and 13 of the bit sampling

gated in and out of a channel card in real time on a bit-

sequence A waveform representation for this condition is

for-bit basis.

shown in A, B, and C in figure 5-6. The other four

channels shown in figure 5-5 also have three used ports

5-44. As described in paragraph 5-30, the data applied

that receive three gated clock signals per bit sampling

to a channel card are converted to a synchronous form.

sequence as indicated in the "ACTIVE CHANNEL

The data bits are clocked out of the channel card by

SAMPLING SEQUENCE" column.

gated clock signals on a bit-by-bit basis: one data bit for

each gated clock signal applied to the channel card.

5-47. The near-homogeneous port sampling sequence

Each gated clock signal generated in the common

shown in figure 5-5 is not random, but is developed by

electronics is equivalent to one bit time in the multiplexer

reversing the 5-digit binary numbers that represent bit

output data stream. Also, the number of gated clock

sampling sequence counts of 1 to 16. Examples of

signals applied to all channel cards, plus the overhead

reversing the binary counts are listed below. For a given

service bits, is equal to the number of data bits in the

configuration, the number of ports used is a selected

multiplexer output data stream over a given period of

number between 15 and 31. When the port addressed

time.

by a reversed binary count is greater than the number of

used ports in the configuration, that specific address is

5-45. The number of ports required to service a given

automatically bypassed and the next applicable port

data channel is based on the formula Rc = KR as

count is generated without any delay. The following

described in paragraphs 5-23 through 5-26. The rate at

example assumes that the system used has 15 used

which gated clock signals are applied to a given active

ports.

The

use

reverse

binary

channel is KR For example, a data channel with a Bit

5-11