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Page Title:
INTEGRATED CIRCUIT DESCRIPTIONS-CONT. |
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 T.O. 31S5-4-308-l
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
stored in the associated latch. When the
C, D, and E (pins 2, 3, 4, 6, and 7)
write 1 input W 1 goes low, the data stored
with a high level load pulse applied to the
in the four latches is coupled to the data
preset enable inputs. Presetting is also
outputs 01 through 04. When the write
independent of the clock input level. The
2 input W2 goes low, the data stored in
data then can be read out in parallel through
the two latches is coupled to the data out-
the outputs QA, QB, QC, QD and QE or
puts 05 and 06. If Wl and/or W2 is held
the register can be clocked with the data
low the associated latches act as high
taken out in serial out of Transfer of infor-
mation to the outputs occurs on the
speed inverters.
positive-going edge of the clock pulse.
The serial input provides the data to the
first R-S flip-flop, which the outputs of
CODER (see figure 145). The SN7442N is
a decoder which translates a 4-bit BCD
the subsequent flip-flops provide informa-
code into on of ten corresponding decimal
tion for the remaining R-S inputs. The
clear input must be high and the preset
outputs. Full decoding of a valid input
enable inputs low when clocking occurs.
number (0 to 9) ensures that one specific
output is low, while all outputs remain off
(high) for all invalid input (10 through 15)
(see figure 148). The SN74100 contains
conditions (see associated truth table).
eight latches used for temporary storage
of binary data between processing units
5 - 7 8 4 . SN7493A, DIVIDE BY 2, 8 or 16
BINARY COUNTER. (see figure 146). The
and input/output or indicator units. The
SN74100 has two enable inputs (pins 12
SN7493A is a four master-slave flip-flop
and 23) each enabling a group of four
binary counter capable of a divide by 2, 8
latches. Four bits at a time can be latched
or 16 count. 3 of the flip-flops are con-
nected for .a divide by 8 count using input
or the enable inputs can be tied together
to latch eight bits at a time. The following
B (pin I) and outputs B, C, D (pins 9, 8
and 11). The flip-flop with input A (pin 14)
description is applicable to all eight
latches. Information present at a data (D)
is a divide by 2 stage and when output A
input is transferred to the Q output when
(pin 13) is connected to input B, a divide
the enable (G) is high and the Q output
formed using input A for the
will follow the data input as long as the
ll four master-slave flip-
e remains high. Whe
o a common gated reset line
goes low, the information,
which inhibits the count and simultaneously
at the data input at the time the transitnon
resets the flip-flops.
occurred, is retained at the Q output until
the enable goes high.
(see figure 147). The SN7496 shift regis-
ter consists of five W-S master-slave flip-
DECODER/DE MULTIPLEXER. (see figure
flops connected to perform parallel-to-
149). The SN74138N is a high-speed
serial or seri -to-parallel conversion of
decoder/demultlplexer used in high speed
ith both inputs and outputs
0 a routing applications. It generates one
flops accessible,
or eight lines that is dependent on the
parallel-in/parallel-out or serial-in/
conditions at the three enable inputs and
serial-out operations may be performed.
three binary select inputs, The enable
win the flip-flops are simultaneously set
inputs are two active-low, G2A and G2B,
ut level with a Bow-level to
and one active high, Gl, to reduce the
preset enable inputs.
need for external gates or inverers when
Clearing is independent of the level of the
expandang. In the decoding mode, inputs
clock input. The register can be parallel
G1, G2A and G2B (pins 6, 4, and 5) are
loaded by using the clear input in conjunc-
tion with the preset inputs. After the
stages are cleared to low level outputs,
ed through preset inputs A, B,
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