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T.O. 31S5-4-308-l
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
driver/receivers U69, U70, U79, and U80.
For a read operation, CROS-P
5-592.
DBRA-P, DBRB-P, and DBRC-P strobes the
(waveform A, figure 89) is generated which
data bus driver/receivers which cause the
enables G13, G14 and G16, as previously
data to be routed to the INFIBUS data lines
discussed.  The Formatter function is
DBOO-N through DB15-N.
notified of a read operation and then the
Formatter function presents data to the
5-590. When the Block Transfer Adapter
Mag Tape Controller. This causes the
is initialized, the Mag Tape Controller is
Mag Tape Controller data input and selec-
slaved by the Block Transfer Adapter to
tor circuit to generate DOOA-N through
present data to the Formatter function or to
D15A-N which is routed to data bus
driver/receivers U69, U70, U79 and U80.
the INFIBUS. The following two paragraphs
The Block Transfer Adapter initiates a DDT
discuss a write and a read operation when
and generates BTA2-N (waveform B, figure
the Block Transfer Adapter in initialized.
89) which is inverted by I13. I13 generates
5-59 1. For a write operation, the Mag
BONA-P (waveform C, figure 89) which en-
Tape Controller is cleared and a write
ables G10, and activates G13, G14 and
G16.  BONA-P is also routed to the Mag
control word is loaded into the control regis-
ter.  This causes WBAS-P (waveform A,
Tape Controller read/write control Stat us
figure 88) and CRlS-P (waveform B, figure
circuit.  G13, G14, and G16 generates
88) to be generated which enables G10, as
DBRA-P, DBRB-P, and DBRC-P, respectively.
previously discussed. The Block Transfer
This strobes data bus drivers/receivers
U69, U70, U79, and U80 which couples the
Adapter performs a DDT which slaves the
data onto the INFIBUS data lines. The
Core Memory Controller to read data from
Block Transfer Adapter then completes the
the Core Memory. Also, the Block Transfer
DDT by slaving the Core Memory Controller
Adapter generates BTA2-N (waveform C,
to write the data into the Core Memory.
figure 88) which is inverted by inverter I13.
The cycle is repeated until all data required
The output of I13, BONA-P, (waveform D,
is transferred.
figure 88) enables G10, G13, G14, and
G16. BONA-P is also routed to the Mag
5 - 5 9 3 .  For a write or read operation, when
Tape Controller read/write control status
all data required is transferred, the Block
circuit.  The Core Memory Controller
Transfer Adapter generates BTA4-N on the
presents data on the INFIBUS and DBOO-N
INFIBUS.  BTA4-N disables G8 and is routed
through DB07-N is inverted and routed to
to the Mag Tape Controller INFIBUS access
output data register U57 by data bus driver/
circuit or CATS-P and the Mag Tape Control-
receivers U69, U70 and U80. When the
ler initiates an interrupt.
DDT is completed, the Mag Tape Controller
INFIBUS access circuit generates BDNA-P
5 - 5 9 4 . When the Mag Tape Controller per-
(waveform E, figure 88) which activates
G10. G10 generates WDBR-N (waveform F,
forms an interrupt, the Mag Tape Controller
figure 88) which triggers and loads output
address (device number) is placed on to the
data register U57 with data. Also, WDRB-N
INFIBUS data lines. The Mag Tape Control-
is routed to the Mag Tape Controller read/
ler INFIBUS access circuit generates BOLA-P
write control status circuit which causes
and BOLA-P activates G13, G14, and G16
WBAS-P to be removed. G10 is disabled
which generate DBRA-P, DBRB-P, and
and WDRB-N is removed. The output of
DBRC-P, respectively. At the same time,
output data register U57 is coupled through
the Mag Tape Controller data input and
data drivers U62 and U63. This action
selector circuit generates D00A-N through
generates ODOO-P through OD07-P which
D15A-N, representing the Mag Tape Con-
troller address, which is couted to the data
is routed to the Formatter Function. The
bus driver/receivers U69, U70, U79) and!
Formatter Function accepts the data
U80.  DBRA-P, DBRB-P, and DBRC-P strobe
and then the cycle is repeated until all
data bus driver/receivers U69, U70, U79,
data required is transferred.
5-86

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