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Page Title:
MAG TAPE CONTROLLER DATA OUTPUT AND CONTROL REGISTER CIRCUIT. |
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 T.O. 31S5-4-308-l
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
circuit generates MPXA-P and MPXB-P,
cult then generates STRA-P (waveform C,
and the Mag Tape Controller INFIBUS ac-
figure 85) which activates G15. The out-
cess circuit generates BOLA-P. Ml through
put of G15 enables gates G13, Gl4 and
G16. The Mag Tape Controller address
M4 couples the lC3 and 2C3 input:; to the
Yl and Y2 outputs, respectively. M5
receiver and recognition circuit then
couples the 1B through 4B inputs to the Yl
generates AMAS-P (waveform D, figure 85)
through Y4 outputs, respectively. This
and AWST-N (waveform E, figure 85).
condition couples the device number,
AMAS-P activates G13 which generates
DNO4-N through DN11-N, to the Mag
DBRA-P (waveform F, figure 85). RWST-N
Tape Controller data output and control
is inverted by inverter I15 which activates
register circuit.
G6 and G16 generates DBRC-P (waveform
G, figure 85). At the same time, the Mag
MAG TAPE CONTROLLER DATA OUT-
Tape Controller data input and selector clr-
PUT AND CONTROL REGISTER CIR-
cuit generates DOOA -N through D15A-N
CUIT.
(representing status data) which are routed
to the data bus driver/receivers U69, U70,
5 - 5 8 2 . Genera 1. T h e M a g T a p e C o n t r o l l e r
U 7 9 , a n d U 8 0 . DBRA-P strobes data bus
data output and control register circuit
driver/receivers U70 and U80 which couples
stores control words which specify read or
DOOA-P through DO5A-N, D08A-N, and
write operations. It also stores data which
DO9A-N to the INFIBUS data lines DBOO-N
is transferred to the Formatter Function.
through DBO5-N, DB08-N, and DB09-N .
DBRC-P strobes data bus driver/receivers
5 - 5 8 3 . Detail Analysis (see figure 83).
U79 which couples D12A-N through D15A-K
When the master reset pulse, MRES-N, is
to the INFIBUS data lines. After the trans-
generated on the INFIBUS, inverter I11 in-
fer is completed, STRA-P is rcmoved which
verts MRES-N and the output of Ill activates
causes the status data to be removed from
gate G9 which generates GRSA-N. GRSA-N
the INFIBUS.
is inverted by inverter I12 which generates
GRSC-P. If the Mag Tape Controller is
slaved to write into its status register, the
Mag Tape Controller address receiver and
recognition circuit generates AWST-N (wave-
form A, figure 84) and AWRT-P (waveform B,
figure 84). AWST-N enables gate G11 and
AWRT-P is inverted by inverter I14 which
a c t i v a t e s G 1 1 . The output of G11 activates
G9 which generates GRSA-N (waveform C,
figure 84) and I12 generates GRSC-P (wave
form D, figure 84). GRSA-N resets control
register U66 (flip-flop FF2 shown) and also,
GRSA-N and GRSC-P are routed to the Mag
Tape Controller read/write control status
circuit. This causes the Mag Tape Control-
ler read/write control status circuit to
generate WBAS-P (waveform E, figure 84)
which enables gate G10.
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