CORE MEMORY CONTROLLER AlA3A8 ADDRESS TRANSFER CIRCUIT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

1, DBEN-P enables G29 for the PLO-P parity

G19, DBEN-P, is high enabling gate G29.

bit (stored in D008-P position) to activate

The Ql output of read/write register U50,

or disable G29. If an error exists in zone 1

R/R-P, is high which enables gate G25

or 2, FF4 will be set as explained

The Core Memory presents the data word to

previously.

the Core Memory Controller data transfer

circuits and will be strobed to the INFIBUS.

CORE MEMORY CONTROLLER

5-330.

The Core Memory Controller data transfer

AlA3A8 ADDRESS TRANSFER CIRCUIT.

circuit generates the same DBOO-P through

DBl5S-P combination of data bits to the ex-

5 - 3 3 1 . General. The Core Memory Control-

clusive-or gates G30, G32, G33, G38,

ler address transfer circuit converts INFIBUS

G39, G43, G44, and G47. If there was no

address to Core Memory address and trans-

error in transferring the data between Core

mits them to the Core Memory.

Memory and Core Memory Controller (loss

of bits or noise injected hits), the same

5 - 3 3 2 . Detail Analysis (see figure 31).

combination of exclusive-or gates will be

Inverter I1 and associated address receivers

disabled or enabled which causes PLO-P

invert the address bits, ABOO-N through

and PHI-P to assume the same logic levels

AB15-N, from the INFIBUS address lines and

as when the data was written into the Core

generates ABOO-P through AR15-P. Address

Memory. At the same time, the Core Mem-

data ABOO-P through AB15-P are routed to

ory generates the parity bits, D008-P and

D017-P, which will have the same levels as

the Core Memory Controller command and

page select circuit, the address selector/

PLO-P and PHI-P. D008-P and D017-P will

driver gates and the address drivers. The

activate or disable G26 or G29 which acti-

Core Memory Controller command and page

vates or disables G28. If the output of G35

select circuit decodes the addresses and

is the same level as the output of G28, ex-

clusive-or gate G36 will be disabled which

determines whether or not the address is a

presents a low to the set input of flip-flop

low order address or page address.

FF4.

5 - 3 3 3 . When a low order Core Memory ad-

5-328. When DONE-N is generated, in-

dress is received, PAGE MODE-P from the

verter I16 inverts DONE-N and generates

Core Memory Controller command and page

DONE-P which activates G25. When DONE-

select circuit is low and PAGE MODE-N is

N is removed, DONE-P is also removed

high. Driver DRl and associated address

which disables G25. The low-to-high out-

drivers will couple ABOl -P through AB12-P

put of G25 triggers FF4 which remains cleared.

to the Core Memory input address lines,

If there was a bit position of the data

AIOO-P through AI11-P. With PAGE MODE-

in error, the output of G35 will be different

P low G2 is disabled which causes AI15-P

from DOO8-P. The high and low inputs to

to remain low for all low order addresses.

G36 will activate it, presenting a high to

PAGE MODE-P (low) will also enable the

the set input of FF4 when FF4 is triggered,

associated address selector/driver gates

it will set. The 0 output of FF4 will acti-

to couple AB13-P through ABl5-P to Core

vate G37 which generates PARERP-P. The

Memory input address lines, AI12-P

exclusive-or gate G42 with the outputs of

through AI14-P.

G26 and G41 operates in the same manner

to set flip-flop FF5 when an error is de-

5 - 3 3 4 . When a page address is received,

tected in the word read out of Core Memory.

the address is first modified then trans-

ferred. The Core Memory Controller com-

5-329. During byte data transfers the error

mand and page select circuit generates

logic operates in a manner similar to word

PAGE MODE-P, PAGE MC3E-N and a com-

transfers, except when data is read out of

bination of PO-P, Pl-P, IJ17-P and IH06-

zone 2 of Core Memory, DCEN-P enables

P which is the page number. ABOl-P

gate G27 for the PI-II-P parity bit (stored in

through AB12-P are coupled through the

D017-P position) to activate or disable G27

address drivers as explained previously.

AB13-P through AB15-P are blocked (PAGE

when data is read out. When reading zone

5-47