CORE MEMORY CONTROLLER AlA3A8 COMMAND AND PAGE SELECT CIRCUIT-CONT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

page number until another page is selected

the Q2 output of command register U35,

and

or system reset, MRES-N, is initiated.

PAGE MODE-N, will go low, PAGE MODE-P

and PAGE MODE-N are routed to the Core

Memory Controller address transfer circuit

5-323. Deleted.

where they enable the stored page number

(PO-P, Pl-N, IH06-P, and IJ17-P) to modify

the incoming address to the Core Memory.

The remainder of the cycle will be identical

to a read or write cycle as explained pre-

viously.

5 - 3 2 6 . When writing a 16-bit data word into

the Core Memory, the Core Memory Control-

ler data transfer circuit will transfer the data'

to the Core Memory and also generate DBOO-P

through DB15-P inputs. DBOO-P through

DB07-P are routed to the exclusive-or gates

G30, G32, G33, and G38 and DB08-P

through DB15-P are routed to exclusive-or

gates G39, G43, G44, and G47. The out-

puts of these gates are routed to the inputs

5-324. Once a page is selected and stored

of exclusive-or gates G31, G34, G40, and

in page register U57, addresses COO0 16

G45 and their outputs are routed to exclusive-

through DFFF l6 are used to read from or

or gates G35 and G41. The data bits (DBOO-P

through DB15-P) will have logic levels de-

write into the selected page. The cycles of

termined by the data to be transferred and

reading or writing words or bytes into the

the exclusive-or gates will be activated or

Core Memory pages are similar to the read

disabled according to these levels. The

and write cycles explained previously ex-

outputs of G35 and G41, PLO-P and PHI-P

cept: for addresses COO0 16 through CFFF l6,

are the parity bits which are routed out to

AB15-P will be high which will enable page

the Core Memory Controller data transfer

command decoder U34 and AB14-P is high

circuit to be placed on the data lines with

which causes the Y4 output of page command

the data word to be transferred to the Core

decoder U34 to go low for this range of ad-

d r e s s e s . For addresses DO00 16 through

Memory.

PLO-P is placed on the 8-bit

data line and PHI-P is placed on the 17-bit

DFFF l6, AB15-P is high enabling page com-

mand decoder U34. AB14-P and AB12-P are

data line for word transfers. During byte

transfers, only DBOO -P through DB07-P are

high and the Y5 output of page command de-

coder U34 is low. In both ranges of these

generated by the Core Memory Controller

data transfer circuit. Only the output of

addresses G2 is activated providing a high

G35, PLO-P, will be used with the byte of

D2 input to command register U35. Gl is

data transferred to the Core Memory. When

disabled for these ranges of addresses. If

the byte of data is placed in zone 1 of the

the address exceeds DFFF 16, the Y6 or Y7

Core Memory, PLO-P is placed on the 8-bit

output of page command decoder U34 will go

data line to the Core Memory. When the

low which activates Gl, providing a low Dl

byte data is placed in zone 2 of the Core

input to command register U35. The Ql out-

Memory, PLO-P is placed on the 17-bit

put of command register U35 will be low and

data line to the Core Memory.

G3 and G5 will be disabled which prevents

the Core Memory Controller from transfer-

When the data word is written into

ring data to or from Core Memory.

5-327.

the Core Memory, the parity bits (PLO-P and

PHI-P) are also written with the data word.

When command register U35 is load-

5-325.

When the same word is read out of the Core

ed with a high D2 input (page mode), as ex-

Memory, the output of I2 BYTE MODE-N is

plained previously, the Q2 output of command

high enabling gate G26 and the output of

5-46