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Page Title: CORE MEMORY CONTROLLER AlA3A8 COMMAND AND PAGE SELECT CIRCUIT-CONT.
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T . O . 31S5-4-308-l
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
5-320. To transfer data into or out of the
Memory Controller data transfer circuit.
Core Memory pages, the Core Memory Con-
The data from the Core Memory is then
troller must be set at the page where trans-
placed on the INFIBUS data lines. The 0
output of FF1 activates G20 generating
fers are to be done.  Under control of the
stored software program, the master func-
DONE-N (waveform G, figure 31), as ex-
tion generates address FFFF l6 on the
plained previously. After a delay, the
master function releases the INFIBUS and
INFIBUS address lines and the number of
the Core Memory Controller is cleared as
the page, 0000 16 to OOOF 16 on the INFIBUS
explained previously.
data lines with RITE-N low. The Core
the data read from the Core Memory is from
Memory Controller address transfer circuit
zone 1 or zone 2. For zone 1, ABOO-P is
generates ABOO-P through AB15-P. Gates
high at the D4 input of command register
G6, G7 and G9 are activated by AB
through AB11-P and their outputs are inverted
U35. When command register U35 is trig-
by inverters I10, Ill and I12 which enables
gered, it will be loaded with high D3 and D4
inputs.  The Q3 output of command register
gate G8. AB15-P enables the page command
U35 is inverted by I2 which disables G12.
decoder U34 and with ABl2-P through AB14-P
high, the Y7 output is low. Gate GI is acti-
The 3 output of command register U35 is low
vated and inverter I9 inverts the low Y7 out-
and inverted by I4 which enables gate G15.
put which activates G8. RITE-N is inverted
The Q4 output of command register U35 is
low and it activates G18 which enables G19.
by I5 which enables gate G11. The page
When G5 is activated as explained previously,
number, DBOO-P through DB03-P, from the
only G19 is activated which generates
Core Memory Controller data transfer circuit
is routed to the Dl through D4 inputs of page
DBEN-P. DBEN-P is routed to the Core Mem-
register U57.
ory Controller data transfer circuit which
causes the zone 1 data from the Core Mem-
ory to be placed on the INFIBUS data lines
5-321. The master function now generates
(DBOO-N through DB07-N).
its strobe, STRB-N, which is inverted by I3.
The output of I13 triggers SSl and enables G21.
5-318. For reading data out of the Core
In 40 nsec SSl resets which clears FF2.
Memory in bytes operation is similar to when
The 1 output of FF2 (low) activates G23 which
a word is to be read from the Core Memory,
enables G22 and the 0 output of FF2 (high)
except the master function will also generate
activates G11.  The output of G11 is inverted
BYTE-N.  I1 inverts BYTE-N and presents a
by inverter I18, generating lF6-1 which trig-
high at the D3 input of the command register
gers page register U57, loading it with the
U35. Address bit ABOO-P will determine if
binary coded page number. Gate G24 is also
activated by the output of G11 which acti-
5-319. Operation during a zone 2 read cycle
vates G20, generating DONE-N.
is similar to a zone 1 read cycle, except the
data stored in zone 2 of the selected address
in the Core Memory is placed on the INFIBUS
5-322. The outputs of page register U57
data lines. When a zone 2 read cycle is re-
represent the page number and activate or
quested, ABOO-P is low and the Q4 output of
disable gates G46 and G48. PO-N through
command register U35 will be high which
P3-N (page number code) are routed to the
enables G15 (G15 will also be enabled by
Core Memory Controller data transfer circuit.
the output of 14). When G5 is activated,
PO-P, Pl-N, IHO6-P, and IJ17-P are routed
as explained previously, only G15 is acti-
to the Core Memory Controller address trans-
vated, generating DCEN-P which is routed
fer circuit where they are used to modify the
to the Core Memory Controller data transfer
page addresses (CO00 16 through DFFF i6) of
circuit. DCEN-P causes the zone 2 data
the selected page. The same range of
read from the Core Memory to be strobed to
INFIBUS addresses is used for each page
the zone one bit positions of the INFIBUS
but the addresses are modified for each
data lines (DBOO-N through DB07-N).
page. Page register U57 stores the selected
5-45

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