CORE MEMORY CONTROLLER AlA3A8 COMMAND AND PAGE SELECT CIRCUIT-CONT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

5-311. After 250 nsec, SS2 resets and the

previously, G17 is activated. The output of

0 output goes high, triggering and setting

G17 is coupled through DR2 generating ZW2-P

F F 3 . The 0 output of FF3 activates gate

(zone 2).

G20 which activates G21. Inverter I14 in-

verts the output of G20 and its output is

5-315. If a read operation of a 16-bit word

delayed by DLl for 50 nsec. Inverter I15

is requested by a master function, the

inverts the output of G21 and its output is

master function presents an address on the

delayed by DL2 for 50 nsec. After the de-

INFIBUS address lines and RITE-N (wave-

lay of DLl, G21 is disabled and after the

form A, figure 31) will remain high. 15 in-

delay of DL2, G22 is activated. The low

verts the high RITE-N input and presents a

output of G21 is inverted by I15 and the high

low D3 input to read/write register U5O.

output of I15 is again delayed by DL2 for

The output of 15 is also inverted by 16 which

50 nsec. Therefore, G22 is activated for

presents a high Dl input to read/write

50 nsec generating DONE-N (waveform G,

figure 30).

5 - 3 1 6 . T h e r-aster function now generates

5 - 3 1 2 . The DONE-N output indicates to

its strobe, STRB-N (waveform B, figure 31).

the master function a completed data trans-

I3 inverts STRB-N which triggers SSl and

f e r . The Core Memory Controller is then

also enables G21. After 40 nsec, SSl re-

reset to the initial condition once again as

sets which triggers command register U35,

explained previously (STRB-N is removed).

loading it with the high Dl input. The Q1

The Core Memory normally cycles in 750

output goes low which activates G23. The

n s e c , writing the word in the addressed

output of G23 enables G22. The Ql output

location, and then generates MEM AVAIL-P

goes high which enables G5 and activates G3.

o n c e a g a i n , enabling the next Core Memory

The output of C3 is inverted by I7 which

cycle to occur.

a c t i v a t e s G 4 . The output of G4 triggers

read/write register U50 and loads it with

5 - 3 1 3 . If the data to be transferred is an

the high Dl input (RITE-N high). At the

8-bit byte, the master function would also

same time, command register U35 Q3 output

generate BYTE-N, and the address bit ABOO-P,

is low which is inverted by I2. The output

being high or low, will determine which zone

of I2 enables gate G12, and the Q3 output is

the Core Memory will write the byte into.

high which is inverted by I4. The output of

Inverter I1 inverts BYTE-N presenting a high

I4 activates gate G18. The output of G18

D3 input to command register U35. Also, if

enables gate G19. When read/write register

the byte is to be written in zone 1, ABOO-P

U50 is triggered, the Ql output goes high

is high presenting a high D4 input to com-

which enables FFl to be set and the Q1 out-

mand register U35. If the byte is to be

put goes low which triggers single-shot SS3.

written into zone 2, ABOO-P is low, presen-

SS3 remains set for 250 nsec, and the output

ting a low D4 input to command register U35.

is coupled through driver DR4 which gen-

When command register U35 is loaded (trig-

erates RD INIT-P (waveform C, figure 31).

gered by SS1), the Q3 output is high which

RD INIT-P commands the Core Memory to

is inverted by I2 generating BYTE MODE-K.

initiate a read cycle.

Also Q3 is low which is inverted by I4 gen-

erating BYTE MODE-P.

5 - 3 1 7 . The Core Memory performs a read

cycle within 300 nsec, presenting data to

5 - 3 1 4 . If ABOO-P is high, the Q4 output of

the Core Memory Controller data transfer

command register U35 will be high which

circuit and generating DATA AVAIL-N (wave-

a c t i v a t e s G 1 3 . The output of G13 enables

form D, figure 31) to indicate data is avail-

a b l e . DATA AVAIL-n' is inverted by inverter

G 1 4 . When SS2 is triggered, as explained

I8 which sets FFl. The 1 output of FFl

previously, G14 is activated. The output of

activates G5 which activates G12 and G19

G14 is coupled through DRl generating ZWl-P

generating DAEN-P (waveform E, figure 31)

( z o n e 1 ) . If ABOO-P is low, the Q4 output of

and DBEN-P (waveform F, figure 31) re-

the command register is high which activates

spectively, which are routed to the Core

G16. When SS2 is triggered, as explained

5-44