CPU CARRY AND OVERFLOW CIRCUIT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

circuit and is inverted by inverter 116 which

5-228. When G3 is activated gate G4 is

generates X1SR-N .

enabled and when G9 is activated, G4 is

activated

The output of G4 and the output

5-223. CPU CARRY AND OVERFLOW

of I5 activates G10 when COUT-P from the

CPU ALU circuit is low. This condition

CIRCUIT.

also enables the set input of FFl, hence,

FF1 is set as explained previously.

5 - 2 2 4 . General. The CPU carry and over-

flow circuit indicates when a carry and/or

5-229. When G11 is activated and T00S-P

overflow condition has occurred. It receives

and STSR-P are generated by the CPU trans-

control data from the CPU microcode reg-

mit register circuit and M12S-P is generated

ister circuit, CPU ALU circuit, CPU trans-

by the CPU ALU input multiplexer circuit,

mit register circuit, CPU register file cir-

G10 is activated. This enables the set

cuit, CPU ALU input multiplexer circuit,

input of FFl, hence, FFl is set as explained

and CPU control circuit. It indicates a

previously.

carry condition to the CPU ALU circuit,

CPU transmit register, and CPU control

5-230. When G11 is activated and the CPU

circuit. Also, an overflow condition is

transmit register circuit generates Tl5S-P

indicated to the CPU control circuit.

and STSL-P G10 is activated which enables

the set input of FF1. FF1 is set as explained

5 - 2 2 5 . Detail Analysis (see figure 22).

previously.

When the CPU ALU circuit generates M32T-P

gate G7 is enabled and inverter I3 inverts

M32T-P which disables gate G9. When the

5 - 2 3 1 . When G7 is activated, gate G6 is

CPU microcode register circuit generates

enabled and when the CPU microcode reg-

M27S-P, gate G8 is enabled and when the

ister circuit generates M26S-P gate Gl is

CPU central timing control circuit generates

enabled and G6 is activated which presets

CKTS-P, G7 is activated. G7 activates G8

F F l . The output of FF1, CRYS-P, activates

which resets flip-flops FFl and FF2.

Gl which activates G2. The output of G2,

CYIN-N, is routed to the CPU ALU circuit.

5-226. When COUT-P is generated by the

CPU ALU circuit gate G10 is enabled and

5 - 2 3 2 . When G5 is activated, the output

inverter I5 inverts COUT-P which disables

of G5 activates gate G14 which enables

G10 and gate G13. When the CPU ALU cir-

gate G13. When the CPU register file cir-

cuit generates M29B-P, gates G3 and G5

cuit generates Xl5S-P, G13 is activated

are activated. G3 activates gate G2 which

which activates gate G16. The output of

generates CYIN-N to the CPU ALU circuit

G16 enables the set input of FF2. When a

and G5 activates G10 which disables the

high-to-low transition output of 16 occurs,

clear input of FFl. Invetter I4 inverts the

FF2 is set which generates OVFS-P. OVFS-P

output of G10 and enables the set input of

is routed to the CPU control circuit to

F F l . When the CPU control circuit gen-

indicate an overflow condition.

erates TSHF-P, gate G11 is activated which

enables gate G12.

5 - 2 3 3 . Inverter I7 enables gate G15 and

when the CPU ALU circuit generates COUT-P

5-227. When the CPU central timing con-

and LBl5-P, G5 is activated and FF2 is

trol circuit generates CKTS-P, G12 is

enabled and set as explained previously.

activated. Inverter I6 inverts the output of

G12 and provides a high at the T input of

5 - 2 3 4 . When G11 is activated, gate G18

F F l . When CKTS-P is removed, G12 is

is enabled and when the CPU transmit

disabled and inserter 16 provides a low to

the T input of FFl. The high-to-low trans-

is activated which enables G18. When the

ition at the T input of FFl triggers and sets

CPU transmit register circuit generates

F F l . FFl generates CRYS-P which is routed

STSL-P, G18 is activated and FF1 is set as

to the CPU transmit register circuit and the

explained previously.

CPU control ciriuit.

5-34