CPU REGISTER FILE CIRCUIT-CONT.

T.O. 3185-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

activated which generates WE47-N. WE47-N

5-217. Detail Analysis (see figure 21).

clocks register files U4, U14, U24, and

U34 to write the data into register R5.

each one-quarter of registers R0 through R3.

5 - 2 2 0 . To read data out of the register files,

each one-quarter of registers R4 through R7

M20S-P and M21S-P from the CPU microcode

and register files U3, U13, U23 and U33

are each one-quarter of registers R8 through

all twelve register files. A binary code from

RB.

zero to three of M20S-P and M21S-P selects

one of four groups of four flip-flops in each

5-2 18. The CPU ALU circuit generates

of the twelve register files. Gates G4, G5,

LBOO-P through LBl5-P which are routed to

and G6 decode M22R-N, M22S-P, M23R-N.

the data inputs (D1 through D4) of the reg-

and M23S-P and are activated by CKRD-P

ister files. LB00-P through LBO3-P are

which generates RE03-N, RE47-N, or

routed to the data inputs of register files

RE8B-N. The output of G4, G5, or G6 se-

U33, U34 and U35 which make up the first

lects and clocks one of three groups of four

4-bit positions of registers RO through RB.

LB04-P through LB07-P are routed to the

U24, U34; or U5, U15, U25, U35) and the

data inputs (Dl through D4) of register files

U23, U24, and U25 which make up the next

data is read from the selected register. For

example, to read from general purpose reg-

4-bit positions of registers R0 through RB.

ister five (R5), the CPU microcode register

LB08-P through LB11-P are routed to the data

circuit generates M20S-P, M22S-P and

inputs (Dl through D4) of register files U13,

M22R-N. With M20S-P high and M2lS-P

U14, and U15 which make up the next 4-bit

low, all twelve register files select the

positions of registers RO through RB. LB12-P

second group of flip-flops (Rl, R5, and R9).

through LBl5-P are routed to the data inputs

M22R-N disables G4 and G6 and M22S-P

(Dl through D4) of register files U3, U4,

enables G5. When the CPU central timing

and US which make up the most significant

control circuit generates CKRD-P, G5 is

4-bit positions of registers RO through RB.

activated which generates RE47-N. RE47-N

5 - 2 1 9 . M21T-P and M20T-P from the CPU

causes the output data (Ql through Q4) of

microcode register circuit are routed to the

WA and WB inputs of all twelve register

be generated.

f i l e s . A binary code from zero to three, of

M20T-P and M2 IT-P, selects one-quarter

5 - 2 2 1 . Inverters 11 through 116 and gates

of each of the twelve register files. Gates

G7 through G22 form latches which latch on

Gl, G2, and G3 decode M22F-N, M22T-P,

low inputs. The Q outputs of the register

M23F-N, and M23T-P and are activated by

files are normally high and the inverters

CKFS-P which generates WE03-N, WE47-N,

activate the gates which holds X00S-P

or WE8B-N. The output of G1, G2, or G3

through Xl5S-P high. When a selected

selects and clocks one of the three groups of

registers Ql output goes low, it is inverted

by 11 which disables G7. When the register

the four register files (U3, U13, U23, U33;

U4, U14, U24, U34; or U5, U15, U25, U35)

is no longer selected, the Ql output returns

and the data, LB00-P through LBl5-P, is

to high but G7 holds the output, X00S-P, low

written into the selected register. For ex-

v i a Il. When XSET-N is generated by the

ample, to write into the general purpose

CPU central timing control circuit all of the

latches are cleared. For example, XSET-N

ister circuit generates M20T-P, M22T-P,

activates G7 and the high output of G7 is

and M22F-N. With M20T-P high and M2lT-P

inverted by 11 which holds G7 activated,

low, all twelve register files select the

second group of flip-flops (Rl, RS, and R9).

5 - 2 2 2 . When a register is selected to read

M22F-N disables Gl and G3 and M22T-P

out data, X00S-P through Xl5S-P are gen-

enables G2. When the CPU central timing

erated to the CPU ALU circuit. Xl5S-P is

control circuit generates CKFS-P, G2 is

also routed to the CPU carry and overflow