Address Generator CCA, (A1O)

TM 32-5865-069-24&P

IDPSEL* and UIRENA* are gated out of the IDPL select logic circuit (U13C) as

IDPLENA*. This signal is used as the output control for registers U16 and U25.

The output from these two registers is IMMEDIATE DATA (IDDAT15-0). The outputs

from the remaining registers are: ADDRESS GENERATOR CONTROL, CONTROL SEQUENCER

INSTRUCTIONs, BUS SELECT, MWRCYC* (MEMORY CONTROL), and PIDLOAD*. These outputs

are controlled by UIRENA*.

3-3.6 Address Generator CCA, (A1O). Refer to figure 3-10, a functional block

diagram of A1O.

A1O receives data from the FFT data busses and generates address

information for A11. Thirty-two bits of IDDAT-BUS and BDAT BUS data are received

by memory data multiplexers (U19A, U25, U26, U37, U38). Sixteen bits of immnediate

data are buffered in U35 & U36. When AIDSEL* occurs, the buffers are enabled

allowing ADAT to be transferred onto the ADAT-BUS. BDAT BUS data is also routed

to multiplier logic circuit (U29, U30, U39, and U40). The data outputs from the

memory data mux are latched into the Memory Data Registers (MDR, U27 and U28) by

AGUCLKB and AGUIR1. The MDR outputs are sent to the Registered Arithmetic Logic

Unit (RALU, U4 thru U7) in 4-bit slices. The RALU receives nine bits (AGU18-0) of

instruction data from A8, four bits (RFA3-0) of read address from the multiplier

registers (used to select one of four registers in the RALU), and four bits of

read/write address from A8. The carry/shift logic circuits (U2, U8, U9, U1O)

receive five bits of shift/carry select (AGUSS2-0) and (AGUCS1-0) inputs from A8.

The outputs from the shift selection logic determine whether the registers in the

RALU shift up or down. A carry signal is generated by the carry select logic.

This is sent to the RALU for arithmetic operations. The data output from the RALU

consists of sixteen bits fed to the permute mux (U14, U15, U23, U24). These bits

are restructured in the permute mux and routed to the memory address register

(U21, U22 and U31, U32). In addition to the data output, four flag outputs are

sent to the processor flag register (U12 and U13). The outputs from the register

are PCARRY, PZERO, POFLW, and PSIGN. Sixteen bits of data are fed out as

MADDR15-O. The output from the permute mux is also fed to the return data

on the next ARDRSEL*.

3-3.7 4K RAM CCA, (A11). Refer to figure 3-11, a functional block diagram of the

All. Sixteen bits of data from the ADAT BUS are fed to the memory. Eight bits

are loaded into the upper byte memory and eight bits are loaded into the lower

byte memory when the memory write logic circuit (U22) generates WRITE ENABLE.

Twelve bits of memory address are applied to the 4K x 16 memory from A1O. The

remaining 4 bits of MADDR are compared by U17 with 4 bits of BOARD ADDRESS. When

there is comparison, CHIP ENABLE is applied to both memory sections. Data from

memory is put on the BDAT Bus via buffers U20 and U21.

3-3.8 1/0 Register Set CCA, (A12). Refer to FO-3, a functional block diagram of

A12. A12 provides the 1/0 functions associated with FFT data processing as

follows:

Collects and decodes data from the CPU (P/O A7) used to control the opera-

tion of the IF down converter A14.

b. Converts ANALOG IN signals from A14 into the digital data required for

signal processing.

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