IDDAT Bus Control

TM 32-5865-069-24&P

3-3.4.1 IDDAT Bus Control. Two control signals IDBSELO and IDBSEL1 are used to

control the bus. These signals are decoded in U36A. The outputs of U36A control

the source of the data enabled onto the bus. When IDCRSEL* is low, buffer U34 and

U35 is enabled. CDAT 15-0 is fed out as IDDAT 15-0. When IDIRSEL* is low, buffer

U27, U29 is enabled. The output of the Macro Instruction Register (MIR) circuit

(U7, U8, U9) is fed onto the bus. When IDRMSEL* is low, the ROM Register Circuit

(U28, U30) is enabled providing data for the bus. The signal IDPLSEL* is fed to

A8 . When IDPLSEL* is low, A8 provides data for the bus.

3-3.4.2 Condition Code Select Logic. The condition code select logic circuit

(U4, U12, and U13) is fed with status signal inputs. These are from the processor

interface A12 via latch U14 and from address aenerator A1O. USOCS 3-O are control

signals used to select the required status signal. The status signal selected

generates CCODE*. CCODE* is applied to controller U23. U23 examines CCODE*

before executing a conditional instruction. CCEN* is normally low. When USQCS

3-O are all high, CCEN* is forced high. This overrides CCODE* for a specific

instruction.

3-3.4.3 Address Control. Data from the FFT data busses is applied to the macro

instruction multiplexer U16, U17, and U18. When control signal USQIR1 is low,

CDAT 11-0 is loaded into the Macro Instruction Register (MIR) formed by U7, U8,

and U9. When USQIR1 is high, BDAT 11-0 is loaded into the MIR. Data is clocked

into the MIR by USQCLK. The MIR output is used to address MIR mapping ROM (PROM

U19-U22). This circuit provides 16-bits of data latched into ROM registers U28

and U30 by USQCLK. The data is enabled onto the IDDAT bus by IDRMSEL*. Twelve

bits of the data word on the IDDAT bus are applied to controller U23. U23

receives a four-bit instruction USQINO-3 from A8. USQINO-3, CCODE*, and CCEN* are

used to process the input data. The twelve-bit address is fed to the micro

address pipeline register and buffer circuit (U24, U25, U31, and U32). This

circuit provides uaddr signals used to address micromemory A8.

3-3.4.4 System Clocks. The clocks used by the FFT processor are generated by the

system clock generator (Y1, U1, U5, U6 and U1O). The clock frequency (6 or 8 MHz)

is controlled by AGUI8. When AGUI8 is low, the clock frequency is 8 MHz. When

AGUI8 is high, the frequency is 6 MHz. CYC* and HOLD* are pulled up on the card.

These functions can also be used to control the clock. CYC* allows single step

during test.

3-3.4.5 A and B Bus Source Decodinq. ABSEL O-3 and BBSEL O-1 are decoded by U36B

and U37 to provide control signals. These signals are used to select the devices

using the A and B data busses.

3-3.4.6 Reset Logic. The reset logic circuit (U1OA, U33) generates an initial

power on reset for the sequencer.

3-3.5 Micromemory CCA, (A8). Refer to figure 3-9, a functional block diagram of

A8 . A8 provides a 2KX80 bit control memory which contains the instructions

required by the data processor. The address (UADDRO-11) from A9 addresses the

memory. Ten bits are used as address inputs to the PROM (U1-U1O). The remaining

two bits are inputs to the board and PROM select logic (U12, U22, U24) in addition

to five bits of BDARD SELECT data. The chip select inputs to the PROM are BRDENA

2* and BRDENA 3* generated by the board select logic. Address bit 11 to the PROM

is BRDENA 1* from the select logic. The 80 bits of instruction from PROM are

latched into the microinstruction registers (U11, U16-U21, U25-U27) by uIRCLK.

Change 1

3-14