Microcomputer (CPU) Section. Refer to FO-2

TM 32-5865-069-24&P

frequency of 3.0 MHz. The output of the filter is applied to switch U2. WBIF*

routes the s gnal thru U2 to the output via switched attenuator U1 and amplifier

When a narrowband signal is required. NBIF* is active and enables local

AR4.

oscillator U1O. The signal from the 'lower"leg of the divider is fed via an exter-

nal bandpass filter to mixer U8. The 1.8 MHz signal from U1O is input to U8 and

down converts the signal. The mixer output is amplified by AR3 and fed thru a

low-pass filter, cut-off frequency 300 kHz, to the input of switch U2. NBIF*

routes the signal thru U2 to the output via U1 and AR4. Video signals, one from

each of the four receivers, are fed to U7. The required signal is routed thru U7

by one of the control signals, VCONT 1* - 4*. The output of U7 is fed thru a

switched 0-50 dB attenuator to AR1. The T-pad attenuators use FET switches U4,

U5, and U6 to obtain a 10 dB per step attenuation. The switches are controlled by

attenuation select signals from A12 (20 DB1-3 and 10 DB). The output of AR1 is

routed thru switch U2 by the VIDEO* 1 signal and output via attenuator U1 and AR4.1

The output from the SP5T switch is routed thru a 20 dB T-pad attenuator. The

output from the attenuator is amplified and buffered in AR4.

3-3.3 RC Bus Interface/8085 CPU CCA, A7. FO-2 is a functional block diagram of

A7 . There are two sections of A7 described in the following paragraphs.

3-3.3.1 Microcomputer (CPU) Section. Refer to FO-2, Sheet 1. The microcomputer

is based on 8085 MPU, U28. U21 and U22 provide four kilobytes of EPROM memory.

One kilobyte of RAM storage is also provided (U1E, U2A, U2B, U12 and U13). The

MPU uses a multiplexed data/address bus. When enabled by ALE, U20 latches the

eight least significant bits of the address from the data/address bus. The more

significant address-bits are buffered by U38. Together, the outputs from U20 and

U38 provide a complete 16-bit address bus. Address bits from U38 are also decoded

by the address decoder circuit (U19, U27) . This circuit provides 15 memory

address/select signals. All 1/0 devices, used to interface the MPU with external

data sources, are accessed using memory mapped 1/0 techniques. The devices are

enabled by signals from two decoders. When enabled by SEL 3000*, U40 decodes

address-bits from the address bus. U40 provides eight device select signals.

These are used to select the required Programmable Peripheral Interface (PPI)

device. Decoder U42 provides eight enable signals, 1/0 SEL O* thru 1/0 SEL 7*.

These are used to enable single 1/0 devices. The read/write logic is controlled

by the signals RD* and WR*. These signals are used to enable data to/from the

data bus. The data bus is buffered to provide a high drive capability. The data

bus buffer circuit (U2C, U3C, U4, U1O, and U11) is bidirectional and controlled by

the RD/WR* and ALE* signals from U18 and U1D. Program instructions for data

collection and distribution routines are stored in the EPROM memory. The power on

reset circuit (CR1, R8, C16) ensures the routines are started correctly at power

on. Interrupt signals TRANSMIT INTR, TIMER INTR and RECEIVE INTR are used to

control program execution. The MPU internal clock is inverted by U9F to provide

the 3.072 MHz CLK* signal. This signal is used to time external circuits pro-

viding data for the CPU.

3-3.3.2 RC Bus Interface Section. The RC bus interface section provides the

functions necessary to interface the RSPU with the RC bus. Refer to FO-2, sheet

2. This section functions under the control of the CPU. Control, address, and

data busses together with 1/0 enable signals interface this section with the

CPU. In turn, the section provides two CPU interrupts for program control. The

RC Bus Interface performs three tasks. These are described in the following

subparagraphs.

3-11

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