Serial Interface Test Function. - TM-32-5811-024-14-P0061

TM 32-5811-024-14&P

test word that has been set on the digital processor test set front panel COMMAND switches into the unit-under-test serial

interface CCA. The 16-bit response word is presented on the digital processor test set OCTAL DISPLAY. The serial

interface test may be activated manually or automatically depending upon the position selected on the SER. INT.

CONTROL AUTO SEND/MAN SEND switch. When AUTO SEND/MAN SEND is in the MAN SEND position, this test

may be activated once by setting the SER INT. SEND switch. The test is automatically repeated at a 1-kHz rate when

the AUTO SEND/MAN SEND switch is in the AUTO SEND position.

When the AUTO SEND/MAN SEND switch is in the MAN SEND position, pressing the SER. INT./SEND switch

provides one 5- start pulse output via AUTO/MAN selector U9A. When AUTO SEND/MAN SEND is in the AUTO

SEND position, U9A delivers continuous start pulses at the 1-kHz clock rate.

The following circuit explanation assumes the AUTO SEND/MAN SEND switch to be in the MAN SEND position (see

figure 5-6). This forces selector U9A to accept a start pulse from synchronizer circuit U15A. Circuit activity occurs in the

following sequence:

(1) Time state T0. Pressing the SER. INT./SEND switch provides a low input to synchronizer circuit U15A via

anti-bounce latch U2 of CCA A5. This allows U15A to respond to one 500-kHz CLK pulse by providing a negative 5-

output pulse.

(2) Time state T1. The negative U15A output pulse is applied to the 16 CLK pulse generator and to the

parallel-to-serial converter via AUTO/MAN selector U9A. This signal at J1 loads the 16-bit test COMMAND word into the

parallel-to-serial converter.

(3) Time state T2. The positive transition of the U9A output (J1) activates the 16 CLK pulse generator.

Activated, the generator responds to the 500-kHz CLK input by providing 16 SHIFT CLK and OUTPUT CLK pulses.

(4) Time state T2+. The SHIFT CLK pulses serially shift data from the parallel-to-serial converter to the unit-

under-test serial interface CCA via test switch U9B and line driver U5A. At the same time, OUTPUT CLK is applied to

the unit under test via U5B and U4B to transfer the data to the receiving serial-to-parallel converter on the unit-under-test

CCA. U5B and U4B are enabled by a low MODE signal output of the handshake logic. U2E and U12B of the handshake

logic respond to the low +IMR-MODE signal from the unit-under-test serial interface CCA by providing this low MODE

signal.

(5) Time state T3. The 16th OUTPUT CLK terminates the test word transfer operation. The unit-under-test

digital processor now extracts the test word from the unit-under-test serial interface CCA and responds to its firmware by

moving to a test acknowledgment routine. The resulting drive to the serial interface CCA provides handshake signals to

the digital processor test set serial interface test CCA A6.

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