Servo Loop Test

TM 32-5811-024-14&P

In addition, the RF processor simulator CCA has a self-test capability. The self-test circuits operate with connector

W240P1 connected to digital processor test set jack J13.

b. Servo Loop Test. The RF processor simulator CCA performs a closed-loop test of the servo by alternately

switching a hardwired DPTS word and a DLP data word, derived from the df control, to a digital-to-analog (d/a) converter.

The resulting d/a outputs are transferred to the df control. A properly operating df control responds to these analog

signals by generating a DLP data word, which equals the DPTS data word, thereby nulling the servo error. This nulling

causes the switched d/a inputs to provide equal analog outputs.

The basic components of the servo loop test circuits are differential line receivers U18A, U18B, and U17A; B serial-

to-parallel converters U19, U20, U21; data select multiplexer U14, U15; d/a converter U16; and bipolar drivers U22A, and

U22B.

The df control responds to the analog signal output of the digital processor test set by applying 24-bit serial data to

differential line receiver U18B. DATA CLK for shifting serial data, and DT MOD for switching the data select multiplexer

are also derived from the df control. The serial-to-parallel converter responds to DATA CLK by converting the serial data

input into a 24-bit parallel output format. All 24 bits are applied to AGE display CCA A2 for presentation on the digital

processor test set COMMAND DISPLAY. Eight DLP and DPTS data bits are applied to the data select multiplexer.

These data consist of seven 1 (high) bits and the most significant bit, the eighth, which is determined by the position of

the front-panel FULL SCALE/HALF SCALE switch (S19). The switch positions and the resulting 8-bit DPTS data word

values are as follows:

Switch position

8-bit DPTS word value

FULL SCALE

255

HALF SCALE

127

The df control for the unit-under-test provides the DT MOD signal, which provides a MUX SELECT square wave at

J2. This signal causes the data select multiplexer to transfer the df control DLP data to the d/a converter when high and

to transfer the DPTS data when low. The d/a converter responds to the 8 bits by driving U22 with an analog output

voltage proportional to the binary value of the input. Figure 5-3 shows the analog 0, 1 outputs that result from the binary

inputs.

c. Self-Test Function. When in the self-test mode of operation, RF processor simulator CCA A5 generates a

hardwired 24-bit DLP and ASC code which is applied to its own differential line receivers (18B) via special test connector

W240P1. Figure 5-4 shows the 24-bit DLP and ASC test code, which is displayed on the digital processor test set

(RESULTING DLP and ASC) COMMAND DISPLAY when the self-test operation is successfully executed.

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