CHAPTER 5 FUNCTIONING OF EQUIPMENT - TM-32-5811-024-14-P0046

TM 32-5811-024-14&P

CHAPTER 5

FUNCTIONING OF EQUIPMENT

Section I. GENERAL

5-1. Scope.

This chapter provides theory of operation for the digital processor test set at simplified block diagram, detailed block

diagram, and detailed schematic diagram levels. The purpose of this chapter is to explain the circuit operation of this

equipment to organizational and intermediate support maintenance personnel.

5-2. Organization.

In addition to the general section, this chapter contains a functional description and a detailed theory of operation

section.

Section II. FUNCTIONAL DESCRIPTION

5-3. General.

The digital processor test set is used for fault isolation and operational verification of the df control, df display, and

communication processor. Fault isolation and operational verification is accomplished by externally controlling the digital

processor (central processor unit or CPU) of the unit under test and simulating associated equipment. For example,

when testing a df control, the digital processor test set simulates an RF processor to the df control servo group. The

digital processor test set also replaces the internal df control instruction ROMs with diagnostic ROMs. The response of

the df control to RF processor simulation and the external diagnostic ROMs can be monitored on the CPU DISPLAY and

COMMAND DISPLAY panels of the digital processor test set. Testing of the df display and communication processor is

accomplished in a similar manner.

5-4. Card Cage Assembly.

(See figure FO-1.) The card cage assembly contains 12 CCAs that, in conjunction with the front-panel assembly

controls, control and monitor the test functions. Table 5-1 lists and describes the functions of the card cage CCAs and

figures FO-7 thru FO-17 show CCA diagnostic buffer schematic diagrams.

5-1