Error Blanking and Detection

TM 11-6625-667-45/NAVAIR 16-30APM123-2/TO 33A1-3-367-22

tial states and three outputs (one is common to the

other two) provide the necessary reset conditions

During system

When mode 1 identity tests are in progress, the

tests in all modes except mode C, line-drive enable

first F1 pulse count causes two of the outputs to

DFF1 is used to conclude the receiver gating

gate on one of the video enable reset gates. The

period in the following manner. Twenty-two

second F1 pulse count removes one output, and the

microseconds after the reply F1 pulse starts down

resulting negative-going voltage resets video en-

the delay line to form comparison pulses, it is

able DFF6. Thus, the receiver gate is disabled

coupled by the MODE switch and M1/M3 ampli-

after the F2 pulse of the second train. During

fier to set DFF1. In this state, DFF1 applies a

emergency tests, the third F1 pulse count causes

reset pulse to video enable DFF6 through the video

two of the outputs to gate on another video-enable

enable reset gating and switching circuits. This

reset gate. The fourth F1 pulse count meets DFF6,

action removes the enable voltage from the receiver

and disables the receiver gate after the F2 pulse

gating circuits. When mode C tests are in progress,

of the fourth train.

the 25-microsecond P3 encoder tap through the

M1/M3 amplifier is used to obtain the video reset

e. Error Blanking and Detection.

pulse. This delayed F1 reply pulse is coupled by

(1) Error blankinq. Refer to figures 2-3 to

the M1/M3 amplifier and video reset switching

2-6 for timing diagrams. The error blanking cir-

and gating circuits to reset DFF6; therefore in

cuit inhibits errors that normally would result

this case, the receiver is gated off 25 microseconds

from the first reply F1 pulse and comparison in-

after the F1 reply pulse.

formation pulses after the first train. As stated

(2) Indentity pulse train (except mode 1).

in c above, the first F1 pulse is not generated for

When the identity tests are in progress, line-drive

comparison at the error detector. This F1 pulse,

enable DFF1 and counter DFF3/DFF4 develop

however, will appear at the error detector from

the video reset pulse by a two-step operation. The

video shaper DSS1. Without an internal] y gen-

first operation is started as in (1) above, by the

erated pulse present, an error set output would nor-

22-microsecond delayed F1 pulse from the M1/M3

mally result. To prevent this condition, the error

amplifier. When the output of the M1/M3 ampli-

blanking circuit is initially set by read delay

fier sets DFF1, it also triggers DFF3/DFF4. An

DSS5, which was triggered by video enable delay

output "from each of these circuits gates on a video

DSS4 (b above). The leading edge of the DSS5

reset gate in the video reset switching and gating

150-microsecond negative pulse performs the set

circuit. The second step in the operation is started

operation 1.8 microsecond after the encoder P3

by the reply I/P pulse. Since DFF1 is set, this

pulse is generated. In a set state. the blanking cir-

pulse is gated by line-drive gates 1 and 2. It is

cuit provides an error inhibit voltage to the error

then coupled by emitter follower A10Q7 (EF) to

detector; therefore, the first reply F1 pulse that

reset DFF1. The trailing edge of the pulse causes

arrives at the error detector does not cause an

this reset. Upon being reset, DFF1 removes its

error set output. After the F1 pulse arrives at the

gating voltage from the video reset gate. This ac-

input of delay line A6DLI to start comparison

tion causes a negative-going signal, which resets

pulse train generation, it is also directed as a

video enable DFF6. Thus, the receiver gate is dis-

trigger to the error blanking circuit. The trigger

abled after the I/P pulse.

resets the blanking circuit, thereby removing the

(3) Mode 1 identity and emergency pulse

error inhibit from the error detector. This blank-

trains. Counter DFF3/DFF4 develops the video

ing operation only applies to the first F1 pulse of

reset for these replies. The counter effectively

any reply signal. When emergency tests are in

counts F1 reply pulses flowing through the delay

progress, three sets of framing pulses follow the

line. These are the trigger pulses coupled by the

first train. In this case. three additional opera-

M1/M3 amplifier from the 22-microsecond delay

tions are used for setting and resetting the blank-

line tap during these operations. With each trig-

ing circuit. When another F1 pulse appears after

ger pulse, the counter changes state. Four sequen-

the first one at the input of delay line A6DLl, it

2-6

Change 3