Decoder Section

TM 11-6625-667-45/NAVAIR 16-30APM123-2/TO 33A1-3-367-22

parison pulse trains. Since the I/P pulse holds the

c. Comparison Pulse Generation. A pulse train

same position as an F1 pulse, this delay line pulse

is generated in the decoder section for comparison

is used for the additional F1 pulse comparison.

with the expected reply train. Comparison of both

The first operation ((1) above) produces the first

signals is performed at the error detector. Basic-

F1 comparison pulse. For mode 1 identity tests,

ally, delay line A6DLI and the comparator gen-

this pulse is compared against the F1 pulse of the

erator and code switching circuits perform the

second pulse train. For emergency tests, this com-

pulse train generation. The pulse trains that can be

parison takes place with the F1 pulse of each set

produced are shown in figure 2-2. The first reply

of framing pulses. After the first train, each ad-

F1 pulse establishes the timing reference for the

ditional F1 reply pulse is used to start compari-

generation of the comparison pulses. One cycle of

son pulse generation. Twenty-two microseconds

pulse generation is used for system tests and iden-

tification of position (I/P) tests (except mode 1).

after the first F1 pulse enters the delay line, an

Two cycles are used for mode 1 I/P tests, and four

Ml pulse is produced (fig. 8-1). This pulse sets

are used for emergency tests.

line drive enable DFF1 and, in turn, enables an-

other F1 pulse to pass to the delay line. The second

(1) System and identity (except mode 1)

F1 pulse produces the second train during mode 1

tests. Timing is shown in figures 2-3 and 2-4.

identity tests, and the first set of framing pulses

Pulse train generation circuits are enabled by the

(F1 and F2) during emergency tests. Using the

decode enable pulse, which also triggers the video

M1 pulse, this operation is repeated two more

enabling operation (b above). This pulse sets

times for emergency tests to produce the other two

line-drive enable DFF1 and resets counter DFF3/

sets of framing pulses for comparison.

DFF4. Line-drive gate 1 is then enabled by DFF1.

The first F1 repIy pulse, from video shaper DSS1

d. Receiver Gate Duration Control. The re-

in the receiver section, is gated by line-drive gates

ceiver gate in the receiver section is controlled by

1 and 2. Gated F1 pulses are coupled by emitter

the state of video enable DFF6 (a above). In its

follower A1OQ7 (EF) to drive delay line A6DL1,

set state, DFF6 enables the gate. The duration of

to reset line-drive enable DFF1, and to trigger

this gating depends on the duration of the ex-

error blanking circuit DFF2. Resetting DFF1 dis-

pected reply train, which is concluded within 5

ables line drive gate 1, thereby preventing the

microseconds after the last expected reply pulse.

gating of other pulses. The action of the blanking

This operation is performed in conjunction with

circuit with respect to the first F1 pulse is de-

the video enable reset switching and gating cir-

scribed in e below. As the pulse flows down the

cuits, and is effected during comparison pulse

delay line, it is tapped off at 14 delay points. Each

train generation (c above). During all tests, ex-

pulse (12 information pulses, F2 pulse, and I/P

cept self-test (para 2-7), the gate is closed by

pulse) is coupled by an emitter follower to the

read delay DSS5 if replies were not received from

comparator pulse generator and code selection cir-

the transponder. The state of the video enable

cuits. Here, the information pulses are selected

reset switching and gating circuits is established

with the aid of front pane] CODF. switches, and a

by the positions of the front, panel MODE and

comparison pulse train is generated. A positive and

FUNCTION switches, One of five different states

negative 0.5-micrsecond pulse is generated for

is established to accommodate five possible signal

each pulse in the train. These pulses are applied

conditions as follows: single pulse train, mode C

to the error detector (d below).

pulse train, identity pulse train (except mode 1),

(2) Mode 1 identity and emergency tests.

mode 1 identity pulse train, and emergency pulse

Timing is shown in figures 2-5 and 2-6. During

train. Refer to figures 2-3 through 26 for timing

mode 1 identity and emergency tests, additional

diagrams.

pulse generation takes place. The first operation is

(1) Signal pulse train and mode (C pulse

similar to that described in (1) above. However,

train. Either of these pulse trains is expected

the additional F1 reply pulses are descoded and

during system tests. A single pulse train is ex-

pected for all modes, except certain mode C tests.

redrive the delay line to generate additional corn-

2-5