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T.O. 31W2-2GSC24-2
TM 11-5805-688-14-1
NAVELEX 0967-LP-545-3010
The switch is set to the MUX OFF position when the
5-585. Self-test signal ST2 is an enable signal to AND
multiplexer is not used or to the DEMUX OFF position
gate U22 when the equipment is in the self-test mode.
when the demultiplexer is not used in the multiplexer set.
When the equipment is not in the self- test mode, signal
The switch allows the diagnostic circuits associated with
ST2 goes low and inhibits AND gate U22. This action, in
the multiplexer or the de- multiplexer cards to be
turn, inhibits the secondary diagnostic function on the
bypassed, preventing faulty error indications when either
display card. An error condition detected by either the
the multiplexer or the demultiplexer is not used.
multiplexer or the demultiplexer AND gate circuits in the
self-test mode generates a low-level inhibit signal to AND
5-583. The operation of the primary diagnostic circuits
gate U22. This condition inhibits a high-level output from
on the display card in the self-test mode is the same as
the OR gate circuit from enabling U22 when an error
that described in the functional block diagram discussion,
condition in the primary diagnostic circuits is detected on
with one exception. The input circuits are biased so that
the display card. This configuration gives the secondary
a low-level error signal input is processed through the
diagnostic circuits the lowest priority status in the self-
circuits as a no- error input and, in turn, a high-level input
test mode.
signal is processed through the circuits as an error input.
5-586. A self-test delay enable circuit on the display
5-584. The secondary diagnostic cir cuits
that
card provides a fixed delay time before the, self-test
supplement the primary diagnostic circuits in the self-test
circuits are activated, preventing an erroneous indication
mode are shown in figure 5-44. The basic concept of the
from being generated at the time the SELF TEST switch
self-test function of the primary diagnostic circuits on the
on the front panel is set to the on (up) position. The
display card is that all the error signal inputs to the
outputs from the two shift registers in the circuit are held
multiplexer and de- multiplexer self-test and function cir-
in the preset condition when signal ST2 is low. When
cuits are in a no-error condition. Thus, high-level enable
the self-test mode is energized, signal ST2 goes high
signals are applied to two of the inputs to AND gate U22.
and enables the. shift registers. At this time, a 0 in the
In turn, when the primary diagnostic circuits are in a no-
count 2 and count 3 outputs inhibits AND gate U36 and
error condition, the output from the card address self-
the multiplexer and demultiplexer channel card error
test OR function circuit is a low-level inhibit signal to one
detector-circuits in the primary diagnostic circuits. Since
input of AND gate U22. If there is a faulty circuit in the
the  functional  operation  of  the  multiplexer  and
primary diagnostic circuits on the display card, the output
demultiplexer shift registers is identical, only the
from the OR circuit goes high and enables AND gate
multiplexer shift register is discussed in the following
U22. AND gate U22, in turn, generates a low-level error
paragraph.
signal that initiates an error display as described in the
following paragraphs.
5-587. The first count is entered in the multiplexer shift
register when word 24 end of scan signal M24EOS2 is
applied as a clock pulse to the register during minor
frame terminal count signal MMF31A-.
5-158

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