Data Retiming Circuits

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

provide sharp cutoff and turn-on characteristics for the

5-386. Data Retiming Circuits.

push-pull emitter followers.

5-387. The multiplexed serial data (MSD) is clocked

5-384. The RC time constant of retriggerable one-shot

through flip-flop U12 by system clock signal R The data

multivibrator U10 in the loss-of-timing activity detector is

are routed through polarity switch S7 to the data output

long enough that the continuous timing pulses through

drivers circuit that generates the balanced or unbalanced

S5 can hold the stage in conduction. When the timing

serial data out signals SDATAO and SDATAO-. The

signals are interrupted, U10 completes its duty cycle and

operation of the data output drivers circuit (Q11 through

its output sets latch U13. Setting latch U13, in turn,

Q17) is functionally the same as that described for the

produces diagnostic loss-of-timing error signal MLOT

timing output drivers circuit. When switch S8 on the card

that is applied to the display card. Self-test signal ST2-

is set to the unbalanced position (U), output signal

is applied to set latch U13 when the SELF TEST switch

SDATAO is tied to ground and SDATAO is +6 vdc.

on the front panel is set to the on (up) position. Reset

When S8 is in the balanced condition (B), signals

signal ERST to the latch circuit is applied when the SELF

SDATAO and SDATAO are +3 vdc signals.

TEST switch is set to the off (down) position. Signal

ERST is also generated when the DISPLAY RESET

5-388. The operation of data error detectors Q18

switch on the front panel is pressed and then released.

through Q20 is functionally the same as that described

When error signal MLOT is generated, the LOSS OF

for the timing error detector circuit. A defective output

MUX TIMING indicator on the front panel lights and

data signal generates a diagnostic error signal from Q20

remains lighted until signal MLOT- is removed.

to the composite OR gate and latch circuits.

5-385. Transistors Q8 and Q9 in the timing error

5-389. Transition Encoder Timing Circuits. Timing

detector circuit are normally off and Q10 is conducting.

oscillator Y2 generates 1.8432-MHz (+0.01 percent)

When signal TIMOUT or the TIMOUT is missing, a

timing signals that are applied to eight-stage N binary

voltage unbalance occurs that forces either Q8 or Q9

counter Ull, U14. The N=6 (28.8 kHz) output from U14-

into conduction. When Q8 or Q9 conducts, Q10 is

13 is applied to divide-by-six counter U16, U18 to

forced into cutoff. When Q10 is cut off, a high-level

produce the 4800-Hz timing signals. These signals are

diagnostic error signal is applied from Q10 to gates U19

routed through three distribution buffer gates U21 to

and U20 in the composite OR gate and latch circuit.

provide the T4800A, T4800B, and T4800C timing

Self-test signal ST2is applied to Q10 when the SELF

outputs. The N=8 (7.2 kHz) output from U14-11 is

TEST switch on the front panel is set to the on (up)

applied to divide-by-two counter U16 to generate the

position.

Signal ST2forces Q10 into cutoff and a

3600-Fz timing signals.

These signals are routed

simulated error signal is applied to the composite OR

through three distribution buffer gates U24 to provide the

gate and latch circuits to test the diagnostic circuit

T3600A, T3600B, and T3600C timing outputs. Timing

function. Transistor Q10 is forced into conduction when

signals T3600A and T4800A are applied to one-shot

the SELF TEST switch is set to the off (down) position.

multivibrators U10 and U15 in the 3600-Hz and 4800-Hz

activity detectors. When one of the timing signals is

interrupted, the associated multivibrator completes its

duty cycle and a diagnostic error signal is applied to

composite OR gate U17, causing signal MRT to be

generated as explained in the following discussion.

5-102