BLOCK DIAGRAM DISCUSSION - TM-11-5805-688-14-10196

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

5-360. System clock signal Ro is applied through system

Overhead address count signals MOH0 through MOH3

clock buffers and is distributed as system clock signals

from the GC/DM card contain the 4-bit channel

MRIO1through MRI08to the channel cards. Clock signal

addresses that select the one channel to be interrogated

MRIO is also derived from signal Ro and is applied to the

in both multiplexers during each minor frame. Positive

GC/DM and sequencer cards.

and negative stuff acknowledge signals MPSA and

MNSA from the two multiplexers are routed back to the

5-361. Positive stuff multiplexer No. 2 and negative stuff

GC/DM card as part of the overhead function. Positive

multiplexer No. 2 are part of the diagnostic function. The

stuff acknowledge signal MPSA from positive stuff

two multiplexers duplicate the outputs of positive and

multiplexer No. 1 is routed to the display card, where the

negative stuff multiplexers No. 1. Diagnostic stuff

signal is interrogated for diagnostic error data during

acknowledge MPSA and MNSA signals from the two

word 24. Self-test signal ST2 is applied through the OFF

diagnostic multiplexers are applied to the diagnostic

positions of the DIAGNOSTICS AND OVERHEAD

comparator,

where they are compared with the

switches to the inactive channel inputs of positive stuff

functional MPSA and MNSA outputs. When the output

multiplexers No. 1 and No. 2 to prevent false diagnostic

signals being compared are not alike, the diagnostic

error indications during the self-test mode.

comparator generates a stuff error signal to the

composite error detector. The composite error detector,

5-358. The word 24 decoder generates word 24 signals

in turn, generates OEG card diagnostic signal MTMOG

when word count signals MWC0, MWC1, MWC2 and

as described in paragraph 5-364.

MWC4 from the GC/DM card are a count 23 and end of-

scan signal EOS2 from the end-of scan decoder is

5-362. The system clock activity detector monitors

generated. The output signals from the decoder are

system clock signal Ro and generates diagnostic loss-of

word 24 signals MW24N1through MW24N4 and word 24

timing error signal MLOT when the signal is missing.

bit 0 signals MW2401through MW2404-. The output

Once the error condition is detected, signal MLOT is

signals are applied to the channel cards and to the frame

applied to the display card until the DISPLAY RESET

sync card. Word 24 end-of-scan signal M24EOS2 from

switch on the front panel is pressed. When the switch is

AND gate U21 is generated and routed to the display

pressed, reset signal ERST is applied to the detector. If

card when the two decoder circuits generate word 24

the malfunction is corrected, the detector returns to its

and EOS2.

no-error state. When the SELF TEST switch on the front

panel is set to the on (up) position, self-test signal ST2is

5-359. The end-of-scan decoder generates end-of-scan

applied to the card and the detector is set to its error

signals EOS2, and EOS3 that represent two levels of the

position until the SELF TEST switch is returned to the off

end-of-scan signal. Each sequential EOS signal is

(down) position. When the SELF TEST switch is set to

separated in time by one R clock time. Signal EOS2 is

the off (down) position, reset signal ERST is

applied to AND gate U21 and to word 24 decoder as an

automatically applied to the card and the detector is reset

enable signal. End-of scan signals MEOS3N1 through

to its no-error state.

MEOS3N4 generated by the decoder are routed to the

channel cards.

5-95