Timing Recovery Function

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

signals down to produce the 30-Hz, 600-Hz, and 1200-

the first- half detector generates a high-level signal to

Hz timing signals applied to the 100, 200, and 400

AND gate U19A when a first- half transition occurs or a

positions of the TE range switch. The selected range,

low-level signal to AND gate U19A when a second-half

which is at least three times the bit rate of the data, is

transition occurs.

routed through the TE range switch and is applied to the

data sample flip-flop, the data transition detector, the 2-

5-211. The 2-bit shift register sequentially clocks out the

bit shift register, and through inverter U24, to the first-half

enable 1 and enable 2 timing signals that are

detector. The selected sampling data rate must be at

synchronized to the TE timing signals. The bit 2 enable

least three times the input data rate, since one bit of data

signal from the shift register enables AND gate U19A so

is coded into three bits.

that bit 2 is sequentially clocked out of U19A to OR gate

U25 by the next TE clock after bit 1 is clocked through

5-209. The incoming data signals (DIXX) are

OR gate U25. In turn, the bit 3 enable signal from the

conditioned in the data receiver and are then applied to

shift register enables AND gate U19B so that bit 3 data

the data sample flip-flop and the first- half detector. The

are sequentially clocked out of U19B to OR gate U25 by

data are clocked through the flip-flop by the selected TE

the next TE clock after bit 2 is clocked out. The 3-bit

timing signals applied through the TE range switch. The

code from OR gate U25 and the TE clock signals

reclocked data are applied to the data transition detector

through inverter U24A are applied to the RCB function.

and to the first-half detector. When a data transition is

detected, the data transition detector generates bit 1 to

5-212. Assuming that there are no further transitions of

signify the transition. The bit 1 pulse, synchronized with

the incoming data over a given period of time, the output

the TE timing signals, is applied through inverter U24

from OR gate U25 returns to a zero level after a 3-bit

and OR gate U25 to the RCB function. The bit 1 signal

code has been generated for the last transition. The

is also applied to the first-half detector and to the 2-bit

return-to-zero action is initiated when both inputs to

shift register.

The data transition detector also

exclusive OR gates U18-8 and U18-11 are either high or

determines if the transition is positive going or negative

low, depending on the type of transition decoded.

going., Bit 3 from the detector is a high-level signal when

the transition is positive going or is a low-level signal

5-213. Timing Recovery Function (Figure 5-17).

when the transition is negative going. The bit 3 signal is

applied to AND gate U19B.

5-214. The

timing

recovery

function

provides

synchronous timing pulses for the incoming data whose

5-210. The first-half detector determines when the data

bit rate is 75, 150, 300, 600, 1200, 2400, 4800, or 9600

pulse transition occurs with respect to the TE timing

bps. The functional circuits maintain bit count integrity

signals. A transition of the data that occurs during the

(provide the proper number of timing pulses) in excess of

high-level portion of the timing signal is identified and

100 data bits when there are no pulse transitions as a

coded as a first half transition. Conversely, a second

result of a continuous stream of l's or O's. The bit count

half transition is defined as a transition that occurs during

integrity

based

the

the low-level portion of the TE timing signal. Therefore,

5-53