Input-Output Data Rate Compare Function

T.O. 31W-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

U9 is held in an enabled state when switch S3 is

effect is that write address latch U25 is enabled at word

strapped in the RCB configuration. When switch S3 is

24 bit 1. For example, at word 24 bit 0, if the read

strapped in the URC configuration, AND gate U9 is

address counter output to the read address latch is 0000,

enabled or inhibited by the output from AND gate U36 in

the write address counter output should be 1000.

the coarse rate conversion circuits. The gated clocks

Therefore, at word 24 bit 1, the read address latch

applied through AND gate U9 increment read address

remains at 0000 and the write address latch is enabled

counter U27. The 4-bit address from U27 is applied to

to accept the write address counter output of 1001. The

holding register U26. The register, in turn, applies a 3--

Q outputs from read address latch U34 are applied to the

bit address to the read address inputs of elastic storage

B inputs of B-C-1 adder U33 and the Q (complementary)

registers U19 and U20. The data bits read out of U19

outputs from write address latch U25 are applied to the C

and U20 are each applied to dual AND-OR gate U39.

inputs of the B-C-1 adder. Therefore, the B inputs to

Inverter U30-6 enables one AND gate of U39 so that

U33 are 0000 and the C inputs to U33 are 0110. The

data are read out of register U20 for bits 0 through 7 and

total implementation conforms to algorithm B-C-2. The

are read out of register U19 for bits 8 through 15.

4-bit output from B-C-1 adder U33 is decoded by AND

Multiplexer system clock signal MRIOX clocks the

gates U31 and U32 to determine if the address

address out of holding register U26 and through output

relationships require a positive stuff, negative stuff, or an

data buffer U38-6 to the OEG card. For each data bit

out-of-tolerance condition. A positive stuff condition is a

applied through data receiver U42-1, one equivalent data

high-level output from AND gate U32-11, a negative stuff

bit is clocked out of output data buffer U38-6.

condition is a high-level output from AND gate U32-3,

and an out-of-tolerance condition is a high-level output

from AND gate U31-10.

The 4-bit binary codes

5-195. Input-Output Data Rate Compare Function.

generated by the B-C-1 adder, together with the resulting

decodes, are listed below.

5-196. In the initialization circuit, J-K flip-flop U16-10

normally has a low-level signal applied to the J-K inputs

5-197. The three outputs from the decoder logic are

so that AND gate U17-6 has an enable input and AND

applied to the stuff comparator U48 as part of the

gate U17-8 has an inhibit input. This condition causes a

diagnostic function. A high-level positive stuff output

rate compare function to be initiated when word 24 bit 0

from AND gate U32-11 is applied to one of the AND

(signal MW240X-) is applied through inverter Ull-8 to

gates in AND-OR gate U39 and is transmitted as signal

AND gate U17-6. The high level signal from Ull-8 is

MPSTXX through the OR gate in U39 when word 24

applied to read address latch U34 so that the output from

signal MW24NX is also applied to the AND gate in U39.

read address counter U27 is latched in U34 at word 24

A high-level negative stuff output from AND gate U32-3

bit 0 (signal MW240X). The low-level signal from U17-6

is applied through inverter U30-8 as signal MNSTXX-.

sets latch U23-3 in the rate compare control circuit. The

Signal MNSTXX or MPSTXX is applied to the OEG card

next timing signal (TIXX) applied through inverter U30-2

for processing when a stuff command is generated.

increments write address counter U18, clocks J-K flip-

High-level

flop U22-9, and enables AND gate U13-4. The total

5-47