TRANSITION DECODER (TD) CARD

T.O. 31W-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

a TE/TR card that was configured for the TE function.

effectively causes the read address count from the read

The original timing associated with the data processed

address counter to track the write address count from

by an RCB card is also reconstructed in the SB card.

the write address counter on a bit-for-bit basis, while

maintaining a difference count of eight between the two

5-128. The incoming data (DTIX-) are clocked through

addresses. The APLL circuit also performs a smoothing

the data input buffer and are written into the data elastic

function to compensate for any abrupt changes in the

storage register. The data input buffer, write address

data bit rate caused by the overhead stuffing function.

counter, and data elastic storage register are clocked by

The output clock signals from the APLL circuit are

gated clock signals DGCO1 from the GC/DM card. The

identical to the read clock signals. The output clock

gated clock signals are applied directly to the buffer, the

signals clock the data bits through the data output buffer

counter, and the storage register when the SB/URD

to the data output drivers. The output clock signals also

switch is in the SB position. When the switch is in the

clock the timing output drivers to produce the

URD position, the gated clock signals are effectively

complementary demultiplexer timing out signals TOXX

applied through the coarse rate conversion (CRC)

and TOXX-. The data bits applied to the data output

circuits to the buffer, the counter, and the storage

drivers are conditioned and processed

into

complementary demultiplexer channel data output

the same as that performed by the CRC circuits in the

signals DOXX and DOXX-.

RCB card used in the multiplexer. The write address

counter is sequentially incremented by each gated clock

5-130.

NARROW BAND SMOOTHING BUFFER

pulse applied to it. The rate at which the write address

(NBSB) CARD.

counter is incremented is, in effect, the nominal bit rate

at which the data will be processed out of the channel

5-131. The NBSB card is identical to the SB card

card. The write addresses from the write address

described in paragraphs 5-126 through 5-129. The

counter enable the data bits to be written into the data

APLL circuit on the NBSB card is physically different, but

elastic storage register. The read addresses that clock

performs the same functions as those described for the

the data out of the data elastic storage register are

APLL circuit on the SB card. The APLL circuit on the

generated by the read address counter. The read

NBSB card is configured to provide a greater smoothing

address counter, in turn, is incremented by the read

action that occurs over a longer period of time as

clock pulses applied from the analog phase-locked loop

described in the detailed theory of operation for the

(APLL) circuit.

NBSB card. The NBSB card has a narrower range of

frequencies that it can process as compared to the SB

5-129. The APLL circuit generates the read clock

card.

pulses that increment the read address counter. The

read address counter, in turn, produces the read

5-132. TRANSITION DECODER (TD) CARD.

address signals that read the data bits out of the data

elastic storage register. Tie APLL circuit contains a

5-133. The TD card receives the high-speed serial data

phase-locked loop configuration that

in the form of synchronous data (DTIX-) from the FS

card. The TD card function is basically the complement

of the TE card function performed on the TE/TR card in

the

multiplexer.

Functionally, the TD card

demultiplexes one channel of data out

5-30