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Page Title: SECTION II MULTIPLEXER, DEMULTIPLEXER, AND OVERALL DIAGNOSTICS FUNCTIONAL BLOCK DIAGRAM DISCUSSIONS
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T.O. 31W2-2GSC24-2
TM 11-5805-688-14-1
NAVELEX 0967-LP-545-3011
SECTION II
MULTIPLEXER, DEMULTIPLEXER, AND OVERALL DIAGNOSTICS
FUNCTIONAL BLOCK DIAGRAM DISCUSSIONS
5-68.  This section contains separate functional block
for the storage register are independent of each other;
diagram discussions for the multiplexer, demultiplexer,
the only restriction is that data written into a given
and overall diagnostics.
The overall diagnostics
address cannot be simultaneously read out of the
functional  block  diagram  discussion  includes  the
address.
diagnostic circuits associated with the multiplexer,
demultiplexer, and power supply.  The block diagram
5-73.  As shown in figure FO-1, digital data signals
discussions of the circuits on the front panel are also
DIXX are applied to a data receiver on the RCB card.
incorporated  into  the  overall  diagnostics  circuit
The data receiver conditions the data into TTL levels
discussion.
compatible with the logic circuits in the multiplexer. The
associated timing signals are applied to a timing receiver
5-69.  OVERALL
MULTIPLEXER
FUNCTIONAL
that conditions the signals into TTL levels.
The
BLOCK DIAGRAM DISCUSSION.
conditioned timing signals are routed to increment the
write address counter. The write address counter, in turn,
5-70.  GENERAL.  A multiplexer configuration uses
generates sequential write addresses that clock the
between 1 and 15 channel option cards to receive up to
conditioned data into the data elastic storage register.
15 channels of asynchronous digital data and/ or voice
The read address counter is sequentially incremented by
data from associated communications links. The three
gated clock signals (MGCO1) that are applied at a port
rate (Rp) nominally the same as the incoming data rate.
types of channel cards that can be used to receive data
The read address counter is offset from the write
in a multiplexer configuration are shown in figure FO-1.
address counter so that the read address selected at any
The block diagram also shows the four common cards in
given time is always delayed from the write address.
a multiplexer configuration that generate the timing and
The data are therefore not simultaneously read in and
control signals that perform the time-division multiplex
out of the register for a given address. The data read out
and overhead service functions for the incoming channel
of the register are applied to the data output buffer. The
data.
data are clocked through the buffer to the GC/DM card
by multiplexer clock signal MRI01-.
5-71.
RATE COMPARISON BUFFER (RCB) CARD.
5-74.  The rate compare and stuff request circuits on
5-72.  The RCB card receives asynchronous data that
the RCB card are part of the multiplexer overhead
are clocked into a temporary storage register by its own
service function to compensate for changes in the
associated timing signals.  At a later time, data are
incoming bit rate. The rate compare circuits detect any
clocked out of the storage register and are routed to the
variation between the incoming bit rate and the
GC/DM card by signals that are synchronous with the
multiplexer timing function. The write and read functions
5-20

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